From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Date: Thu, 30 May 2019 07:59:07 +0800 From: "jay.xu@rock-chips.com" Subject: Re: Re: [PATCH v2 1/1] arm64: dts: rockchip: add core dtsi file for RK3399Pro SoCs References: <20190528044850.23703-1-jay.xu@rock-chips.com>, <20190529074752.19388-1-jay.xu@rock-chips.com>, Mime-Version: 1.0 Message-ID: <2019053007590678155341@rock-chips.com> Content-Type: multipart/alternative; boundary="----=_001_NextPart788027825660_=----" To: "manivannan.sadhasivam" Cc: =?UTF-8?B?SGVpa29TdMO8Ym5lcg==?= , "mark.rutland" , robh+dt , =?UTF-8?B?5byg5b+X5p2w77yI5Yib5paw77yJ?= , linux-rockchip , linux-arm-kernel , linux-kernel , devicetree List-ID: This is a multi-part message in MIME format. ------=_001_NextPart788027825660_=---- Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: base64 SGkgbWFuaXZhbm5hbi5zYWRoYXNpdmFtLA0KDQoNCg0KamF5Lnh1QHJvY2stY2hpcHMuY29tDQog DQpGcm9tOiBNYW5pdmFubmFuIFNhZGhhc2l2YW0NCkRhdGU6IDIwMTktMDUtMjkgMjA6NTcNClRv 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= Hi maniva= nnan.sadhasivam,

=0A
jay.xu@= rock-chips.com
=0A
 
=
Date: 2019= -05-29 20:57
Subject: Re: [PATCH = v2 1/1] arm64: dts: rockchip: add core dtsi file for RK3399Pro SoCs
<= /div>
Hi, 

Thanks= for the patch. 

O= n top of Heiko's review:

On Wed, 29 May, 2019, 1:18 PM Jianqun = Xu, <jay.xu@rock-chips.com= > wrote:
This patch adds core = dtsi file for Rockchip RK3399Pro SoCs,
=0Ainclude rk3399.dtsi. Also ena= ble these nodes:
=0A- pcie/pcie_phy
=0A- sdhci/sdio/emmc/sdmmc
= =0A
=0ASigned-off-by: Jianqun Xu <jay.xu@rock-chips.com><= br>=0A---
=0Achanges since v1:
=0A- remove dfi and dmc
=0A
=0A=  arch/arm64/boot/dts/rockchip/rk3399pro.dtsi | 74 +++++++++++++++++++= ++
=0A 1 file changed, 74 insertions(+)
=0A create mode 10= 0644 arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
=0A
=0Adiff --git a= /arch/arm64/boot/dts/rockchip/rk3399pro.dtsi b/arch/arm64/boot/dts/rockchi= p/rk3399pro.dtsi
=0Anew file mode 100644
=0Aindex 000000000000..b6d4= 33ffa67d
=0A--- /dev/null
=0A+++ b/arch/arm64/boot/dts/rockchip/rk33= 99pro.dtsi
=0A@@ -0,0 +1,74 @@
=0A+// SPDX-License-Identifier: (GPL-= 2.0+ OR MIT)
=0A+// Copyright (c) 2019 Fuzhou Rockchip Electronics Co.,= Ltd.
=0A+
=0A+#include "rk3399.dtsi"
=0A+
=0A+/ {
=0A+&nbs= p;      compatible =3D "rockchip,rk3399pro";
=0A+
=0A= +       xin32k: xin32k {
=0A+      &= nbsp;        compatible =3D "fixed-clock";
=0A+&nbs= p;              clock-frequency =3D <= ;32768>;
=0A+               = clock-output-names =3D "xin32k";
=0A+         =      #clock-cells =3D <0>;
=0A+    &nbs= p;  };
=0A+};
=0A+
=0A+&emmc_phy {
=0A+    =    status =3D "okay";
=0A+};
=0A+
=0A+&pcie_phy {=0A+       status =3D "okay";
=0A+};
=0A+
= =0A+&pcie0 {
=0A+       ep-gpios =3D <&g= pio0 RK_PB4 GPIO_ACTIVE_HIGH>;
=0A+       num-la= nes =3D <4>;
=0A+       pinctrl-names =3D "de= fault";
=0A+       pinctrl-0 =3D <&pcie_clkr= eqn_cpm>;
=0A+       status =3D "okay";
=0A+}= ;

So, this is for the NPU inside the soc? If yes, then probably only pcie = nodes should be present in rk3399pro.dtsi and others should be in respecti= ve board dts. 

ok,= thanks for your tips.

= Thanks, 
Mani
=0A+
=0A= +&sdhci {
=0A+       bus-width =3D <8>;=0A+       mmc-hs400-1_8v;
=0A+    &nbs= p;  supports-emmc;
=0A+       non-removable;=0A+       keep-power-in-suspend;
=0A+  &nbs= p;    mmc-hs400-enhanced-strobe;
=0A+      &nb= sp;status =3D "okay";
=0A+};
=0A+
=0A+&sdio0 {
=0A+  =      clock-frequency =3D <150000000>;
=0A+  &= nbsp;    clock-freq-min-max =3D <200000 150000000>;
=0A= +       supports-sdio;
=0A+      &nb= sp;bus-width =3D <4>;
=0A+       disable-wp;<= br>=0A+       cap-sd-highspeed;
=0A+    &= nbsp;  cap-sdio-irq;
=0A+       keep-power-in-= suspend;
=0A+       mmc-pwrseq =3D <&sdio_pw= rseq>;
=0A+       non-removable;
=0A+  &= nbsp;    num-slots =3D <1>;
=0A+      &n= bsp;pinctrl-names =3D "default";
=0A+       pinctrl= -0 =3D <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
=0A+ = ;      sd-uhs-sdr104;
=0A+       sta= tus =3D "okay";
=0A+};
=0A+
=0A+&sdmmc {
=0A+   =    clock-frequency =3D <150000000>;
=0A+    =    clock-freq-min-max =3D <400000 150000000>;
=0A+ = ;      supports-sd;
=0A+       bus-w= idth =3D <4>;
=0A+       cap-mmc-highspeed;=0A+       cap-sd-highspeed;
=0A+    &n= bsp;  disable-wp;
=0A+       num-slots =3D <= ;1>;
=0A+       vqmmc-supply =3D <&vccio_= sd>;
=0A+       pinctrl-names =3D "default";
= =0A+       pinctrl-0 =3D <&sdmmc_clk &sdmmc= _cmd &sdmmc_cd &sdmmc_bus4>;
=0A+       = status =3D "okay";
=0A+};
=0A--
=0A2.17.1
=0A
=0A
=0A=0A
=0A
=0A= ------=_001_NextPart788027825660_=------