From mboxrd@z Thu Jan 1 00:00:00 1970 From: Kishon Vijay Abraham I Subject: [RFC PATCH 22/30] PCI: cadence: Configure pci_epc_features to align BAR addresses to 256 Bytes Date: Tue, 4 Jun 2019 18:45:08 +0530 Message-ID: <20190604131516.13596-23-kishon@ti.com> References: <20190604131516.13596-1-kishon@ti.com> Mime-Version: 1.0 Content-Type: text/plain Return-path: In-Reply-To: <20190604131516.13596-1-kishon@ti.com> Sender: linux-kernel-owner@vger.kernel.org To: Tom Joseph , Bjorn Helgaas , Rob Herring , Mark Rutland , Lorenzo Pieralisi , Arnd Bergmann , Gustavo Pimentel Cc: Greg Kroah-Hartman , Frank Rowand , Jingoo Han , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Kishon Vijay Abraham I List-Id: devicetree@vger.kernel.org Cadence PCIe controller has BITS[7:0] of the Inbound Address Translation Units AXI address reserved for special purpose. In order to accommodate this constraint, BAR addresses should be aligned to 256 Byte addresses. Configure pci_epc_features to align BAR addresses to 256 Bytes here. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/pcie-cadence-ep.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/controller/pcie-cadence-ep.c b/drivers/pci/controller/pcie-cadence-ep.c index 3dc1a896c1e6..25638af7c668 100644 --- a/drivers/pci/controller/pcie-cadence-ep.c +++ b/drivers/pci/controller/pcie-cadence-ep.c @@ -484,6 +484,7 @@ static const struct pci_epc_features cdns_pcie_epc_features = { .linkup_notifier = false, .msi_capable = true, .msix_capable = false, + .align = 256, }; static const struct pci_epc_features cdns_pcie_epc_vf_features = { -- 2.17.1