From mboxrd@z Thu Jan 1 00:00:00 1970 From: Maxime Ripard Subject: Re: [PATCH v4 04/13] media: rc: sunxi: Add RXSTA bits definition Date: Wed, 5 Jun 2019 22:00:20 +0200 Message-ID: <20190605200020.tmyom3lg3inu6vvf@flea> References: <20190604162959.29199-1-peron.clem@gmail.com> <20190604162959.29199-5-peron.clem@gmail.com> <20190605095141.psrq6mhk63zto77s@flea> Reply-To: maxime.ripard-LDxbnhwyfcJBDgjK7y7TUQ@public.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Return-path: Sender: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org Content-Disposition: inline In-Reply-To: List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: =?utf-8?B?Q2zDqW1lbnQgUMOpcm9u?= Cc: Mauro Carvalho Chehab , Rob Herring , Mark Rutland , Chen-Yu Tsai , linux-media-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, devicetree , linux-arm-kernel , linux-kernel , linux-sunxi List-Id: devicetree@vger.kernel.org On Wed, Jun 05, 2019 at 02:44:06PM +0200, Cl=C3=A9ment P=C3=A9ron wrote: > Hi Maxime, > > On Wed, 5 Jun 2019 at 11:51, Maxime Ripard wr= ote: > > > > On Tue, Jun 04, 2019 at 06:29:50PM +0200, Cl=C3=A9ment P=C3=A9ron wrote= : > > > We are using RXINT bits definition when looking at RXSTA register. > > > > > > These bits are equal but it's not really proper. > > > > > > Introduce the RXSTA bits and use them to have coherency. > > > > > > Signed-off-by: Cl=C3=A9ment P=C3=A9ron > > > --- > > > drivers/media/rc/sunxi-cir.c | 18 ++++++++++++------ > > > 1 file changed, 12 insertions(+), 6 deletions(-) > > > > > > diff --git a/drivers/media/rc/sunxi-cir.c b/drivers/media/rc/sunxi-ci= r.c > > > index 0504ebfc831f..572bd2257d35 100644 > > > --- a/drivers/media/rc/sunxi-cir.c > > > +++ b/drivers/media/rc/sunxi-cir.c > > > @@ -48,11 +48,11 @@ > > > > > > /* Rx Interrupt Enable */ > > > #define SUNXI_IR_RXINT_REG 0x2C > > > -/* Rx FIFO Overflow */ > > > +/* Rx FIFO Overflow Interrupt Enable */ > > > #define REG_RXINT_ROI_EN BIT(0) > > > -/* Rx Packet End */ > > > +/* Rx Packet End Interrupt Enable */ > > > #define REG_RXINT_RPEI_EN BIT(1) > > > -/* Rx FIFO Data Available */ > > > +/* Rx FIFO Data Available Interrupt Enable */ > > > #define REG_RXINT_RAI_EN BIT(4) > > > > > > /* Rx FIFO available byte level */ > > > @@ -60,6 +60,12 @@ > > > > > > /* Rx Interrupt Status */ > > > #define SUNXI_IR_RXSTA_REG 0x30 > > > +/* Rx FIFO Overflow */ > > > +#define REG_RXSTA_ROI BIT(0) > > > +/* Rx Packet End */ > > > +#define REG_RXSTA_RPE BIT(1) > > > +/* Rx FIFO Data Available */ > > > +#define REG_RXSTA_RA BIT(4) > > > > I'm fine with it on principle, but if the consistency needs to be > > maintained then we could just reuse the above defines > > There is no comment why we can reuse them, they can also be some wrong > case for example the RXINT_DRQ_EN bit is not present in RXSTA and same > for STAT bit present in RXSTA and not present in RXINT. > > I have discover and read this code a month ago and this logic is > really not obvious nor explain. > > Maybe this hack could be done when we will introduce a quirks, but for > the moment I really think that it's more proper and readable to > introduce them properly. I don't think we understood each other :) I was talking about having something like #define REG_RXSTA_ROI REG_RXINT_ROI_EN Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com --=20 You received this message because you are subscribed to the Google Groups "= linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an e= mail to linux-sunxi+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gmane.org To view this discussion on the web, visit https://groups.google.com/d/msgid= /linux-sunxi/20190605200020.tmyom3lg3inu6vvf%40flea. For more options, visit https://groups.google.com/d/optout.