From mboxrd@z Thu Jan 1 00:00:00 1970 From: =?UTF-8?q?Cl=C3=A9ment=20P=C3=A9ron?= Subject: [PATCH v5 01/13] dt-bindings: media: sunxi-ir: Add A31 compatible Date: Sat, 8 Jun 2019 01:10:48 +0200 Message-ID: <20190607231100.5894-2-peron.clem@gmail.com> References: <20190607231100.5894-1-peron.clem@gmail.com> Reply-To: peron.clem-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Return-path: Sender: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org In-Reply-To: <20190607231100.5894-1-peron.clem-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: Mauro Carvalho Chehab , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-media-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, =?UTF-8?q?Cl=C3=A9ment=20P=C3=A9ron?= , Sean Young List-Id: devicetree@vger.kernel.org Allwinner A31 has introduced a new memory mapping and a reset line. The difference in memory mapping are : - In the configure register there is a new sample bit and Allwinner has introduced the active threshold feature. - In the status register a new STAT bit is present. Note: CGPO and DRQ_EN bits are removed on A31 but present on A13 and on new SoCs like A64/H6. This is actually not an issue as these bits are togglable and new SoCs have a dedicated bindings. Introduce this bindings to make a difference since this generation. And declare the reset line required since A31. Signed-off-by: Cl=C3=A9ment P=C3=A9ron Acked-by: Sean Young Acked-by: Maxime Ripard --- Documentation/devicetree/bindings/media/sunxi-ir.txt | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/media/sunxi-ir.txt b/Documen= tation/devicetree/bindings/media/sunxi-ir.txt index 278098987edb..2e59a32a7e33 100644 --- a/Documentation/devicetree/bindings/media/sunxi-ir.txt +++ b/Documentation/devicetree/bindings/media/sunxi-ir.txt @@ -1,16 +1,21 @@ Device-Tree bindings for SUNXI IR controller found in sunXi SoC family =20 Required properties: -- compatible : "allwinner,sun4i-a10-ir" or "allwinner,sun5i-a13-ir" +- compatible : + "allwinner,sun4i-a10-ir" + "allwinner,sun5i-a13-ir" + "allwinner,sun6i-a31-ir" - clocks : list of clock specifiers, corresponding to entries in clock-names property; - clock-names : should contain "apb" and "ir" entries; - interrupts : should contain IR IRQ number; - reg : should contain IO map address for IR. =20 +Required properties since A31: +- resets : phandle + reset specifier pair + Optional properties: - linux,rc-map-name: see rc.txt file in the same directory. -- resets : phandle + reset specifier pair - clock-frequency : IR Receiver clock frequency, in Hertz. Defaults to 8 = MHz if missing. =20 --=20 2.20.1 --=20 You received this message because you are subscribed to the Google Groups "= linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an e= mail to linux-sunxi+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gmane.org To view this discussion on the web, visit https://groups.google.com/d/msgid= /linux-sunxi/20190607231100.5894-2-peron.clem%40gmail.com. For more options, visit https://groups.google.com/d/optout.