Devicetree
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From: Maxime Ripard <maxime.ripard-LDxbnhwyfcJBDgjK7y7TUQ@public.gmane.org>
To: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
	Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>,
	Linus Walleij
	<linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
	devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-gpio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org
Subject: Re: [PATCH v2 11/11] ARM: dts: sun8i: s3: add devicetree for Lichee zero plus w/ S3
Date: Tue, 11 Jun 2019 16:32:39 +0200	[thread overview]
Message-ID: <20190611143239.zvganlwaiku3bs63@flea> (raw)
In-Reply-To: <20190611140940.14357-12-icenowy-h8G6r0blFSE@public.gmane.org>

[-- Attachment #1: Type: text/plain, Size: 2519 bytes --]

Hi,

On Tue, Jun 11, 2019 at 10:09:40PM +0800, Icenowy Zheng wrote:
> Lichee zero plus is a core board made by Sipeed, which includes on-board
> TF slot or SMT SD NAND, and optional SPI NOR or eMMC, a UART debug
> header, a microUSB slot and a gold finger connector for expansion. It
> can use either Sochip S3 or Allwinner S3L SoC.
>
> Add the basic device tree for the core board, w/o optional onboard
> storage, and with S3 SoC.
>
> Signed-off-by: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
> ---
> New patch in v2.
>
>  arch/arm/boot/dts/Makefile                    |  1 +
>  .../boot/dts/sun8i-s3-lichee-zero-plus.dts    |  8 ++++
>  .../dts/sun8i-s3-s3l-lichee-zero-plus.dtsi    | 39 +++++++++++++++++++
>  3 files changed, 48 insertions(+)
>  create mode 100644 arch/arm/boot/dts/sun8i-s3-lichee-zero-plus.dts
>  create mode 100644 arch/arm/boot/dts/sun8i-s3-s3l-lichee-zero-plus.dtsi
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 5559028b770e..2b5e6a1d20ff 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -1110,6 +1110,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
>  	sun8i-r16-nintendo-super-nes-classic.dtb \
>  	sun8i-r16-parrot.dtb \
>  	sun8i-r40-bananapi-m2-ultra.dtb \
> +	sun8i-s3-lichee-zero-plus.dtb \
>  	sun8i-t3-cqa3t-bv3.dtb \
>  	sun8i-v3s-licheepi-zero.dtb \
>  	sun8i-v3s-licheepi-zero-dock.dtb \
> diff --git a/arch/arm/boot/dts/sun8i-s3-lichee-zero-plus.dts b/arch/arm/boot/dts/sun8i-s3-lichee-zero-plus.dts
> new file mode 100644
> index 000000000000..7d2f6b145190
> --- /dev/null
> +++ b/arch/arm/boot/dts/sun8i-s3-lichee-zero-plus.dts
> @@ -0,0 +1,8 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2019 Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
> + */
> +
> +/dts-v1/;
> +#include "sun8i-s3.dtsi"
> +#include "sun8i-s3-s3l-lichee-zero-plus.dtsi"
> diff --git a/arch/arm/boot/dts/sun8i-s3-s3l-lichee-zero-plus.dtsi b/arch/arm/boot/dts/sun8i-s3-s3l-lichee-zero-plus.dtsi
> new file mode 100644
> index 000000000000..bb148e796df7
> --- /dev/null
> +++ b/arch/arm/boot/dts/sun8i-s3-s3l-lichee-zero-plus.dtsi
> @@ -0,0 +1,39 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2019 Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
> + */
> +
> +#include "sunxi-common-regulators.dtsi"

If possible, you should get rid of that include. What are you using it
for?

Maxime

--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

  parent reply	other threads:[~2019-06-11 14:32 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-06-11 14:09 [PATCH v2 00/11] Support for Allwinner V3/S3L and Sochip S3 Icenowy Zheng
     [not found] ` <20190611140940.14357-1-icenowy-h8G6r0blFSE@public.gmane.org>
2019-06-11 14:09   ` [PATCH v2 01/11] dt-bindings: pinctrl: add missing compatible string for V3s Icenowy Zheng
     [not found]     ` <20190611140940.14357-2-icenowy-h8G6r0blFSE@public.gmane.org>
2019-06-12 12:11       ` Linus Walleij
2019-06-11 14:09   ` [PATCH v2 02/11] dt-bindings: pinctrl: add compatible string for Allwinner V3 pinctrl Icenowy Zheng
     [not found]     ` <20190611140940.14357-3-icenowy-h8G6r0blFSE@public.gmane.org>
2019-06-12 12:12       ` Linus Walleij
2019-06-11 14:09   ` [PATCH v2 03/11] pinctrl: sunxi: v3s: introduce support for V3 Icenowy Zheng
     [not found]     ` <20190611140940.14357-4-icenowy-h8G6r0blFSE@public.gmane.org>
2019-06-11 14:27       ` Maxime Ripard
2019-06-12  7:16       ` Paul Kocialkowski
2019-06-11 14:09   ` [PATCH v2 04/11] clk: sunxi-ng: v3s: add the missing PLL_DDR1 Icenowy Zheng
2019-06-11 14:09   ` [PATCH v2 05/11] dt-bindings: clk: sunxi-ccu: add compatible string for V3 CCU Icenowy Zheng
2019-06-11 14:09   ` [PATCH v2 06/11] clk: sunxi-ng: v3s: add Allwinner V3 support Icenowy Zheng
2019-06-11 14:09   ` [PATCH v2 07/11] dt-bindings: vendor-prefixes: add SoChip Icenowy Zheng
2019-06-11 14:09   ` [PATCH v2 08/11] ARM: sunxi: dts: s3/s3l/v3: add DTSI files for S3/S3L/V3 SoCs Icenowy Zheng
2019-06-11 14:09   ` [PATCH v2 09/11] dt-bindings: vendor-prefixes: add Sipeed Icenowy Zheng
2019-06-11 14:09   ` [PATCH v2 10/11] dt-bindings: arm: sunxi: add binding for Lichee Zero Plus core board Icenowy Zheng
2019-06-11 14:09   ` [PATCH v2 11/11] ARM: dts: sun8i: s3: add devicetree for Lichee zero plus w/ S3 Icenowy Zheng
     [not found]     ` <20190611140940.14357-12-icenowy-h8G6r0blFSE@public.gmane.org>
2019-06-11 14:32       ` Maxime Ripard [this message]
2019-06-12 12:14   ` [PATCH v2 00/11] Support for Allwinner V3/S3L and Sochip S3 Linus Walleij

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