Re: [PATCH v2 1/2] Documentation: can: flexcan: Add flexcan clocks' information

[Rob Herring <robh@kernel.org>]

On Thu, May 16, 2019 at 08:12:26AM +0000, Pankaj Bansal wrote:
> The clocking information is missing from flexcan device tree bindings.
> This information is needed to be able to use flexcan. Document the same.

'dt-bindings: can: ...' for the subject.

> 
> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
> ---
> 
> Notes:
>     Dependencies:
>     - https://lore.kernel.org/patchwork/cover/1024536/
>     
>     V2:
>     - Removed clock-frequency from optional properties
>     - Added Dependencies in Notes
> 
>  .../bindings/net/can/fsl-flexcan.txt         | 46 +++++++++++++++++-
>  1 file changed, 44 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt b/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt
> index a04168605998..73c616ca0f9a 100644
> --- a/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt
> +++ b/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt
> @@ -12,9 +12,42 @@ Required properties:
>  - reg : Offset and length of the register set for this device
>  - interrupts : Interrupt tuple for this device
>  
> -Optional properties:
> +Clocking information is must for flexcan. please refer below info for
> +understanding clocking in flexcan:
> +
> +• The FLEXCAN module is divided into two blocks. Controller host interface
> +  ("CHI") and Protocol Engine ("PE")
> +• Both these blocks require clock.
> +• CHI is responsible for registers read write including MB read/write.
> +  While PE is responsible for Transfer/receive data on CAN bus.
> +• The clocks feeding to these two blocks can be synchronous (i.e. same clock)
> +  or asynchronous (i.e. separate clocks).
> +• Selection is made in the CLK_SRC bit (bit 13) of Control 1 Register.
> +  - CLK_SRC = 0, asynchronous i.e. separate clocks for CHI and PE
> +  - CLK_SRC = 1, synchronous i.e. CHI clock is used for PE and PE
> +                 clock is not used.
> +• If this bit is not implemented in SOC, then SOC only supports asynchronous
> +  clocks.
> +• Either of the clock can be generated by any of the clock source.
> +• When the two clocks are asynchronous, then following restrictions apply to
> +  PE clock.
> +  - PE clock must be less than CHI clock.
> +• If low jitter is required on CAN bus, dedicated oscillator can be used to
> +  provide PE clock, but it must be less than CHI clock.
> +
> +Base on above information clocking info in flexcan can be defined in two ways:

s/Base/Based/

> +
> +Method 1(Preferred):
> +  - clocks: phandle to the clocks feeding the flexcan. Two can be given:
> +    - "ipg": Protocol Engine clock
> +    - "per": Controller host interface clock
> +  - clock-names: Must contain the clock names described just above.
>  
> -- clock-frequency : The oscillator frequency driving the flexcan device
> +Method 2(Not Preferred):
> +  - clock-frequency : The synchronous clock frequency supplied to both
> +  Controller host interface and Protocol Engine
> +
> +Optional properties:
>  
>  - xceiver-supply: Regulator that powers the CAN transceiver
>  
> @@ -47,5 +80,14 @@ Example:
>  		interrupts = <48 0x2>;
>  		interrupt-parent = <&mpic>;
>  		clock-frequency = <200000000>; // filled in by bootloader
> +	};
> +
> +	can@2180000 {
> +		compatible = "fsl,lx2160ar1-flexcan";
> +		reg = <0x0 0x2180000 0x0 0x10000>;
> +		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&sysclk>, <&clockgen 4 7>;
> +		clock-names = "ipg", "per";
>  		fsl,clk-source = <0>; // select clock source 0 for PE
> +		status = "disabled";

Don't show status in examples.

>  	};
> -- 
> 2.17.1
>