From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Date: Mon, 24 Jun 2019 09:57:09 +0800 From: "jay.xu@rock-chips.com" Subject: Re: Re: [PATCH v3 1/1] arm64: dts: rockchip: add core dtsi file for RK3399Pro SoCs References: <20190529074752.19388-1-jay.xu@rock-chips.com>, <20190530000848.28106-1-jay.xu@rock-chips.com>, <3309819.J5kelTtX6q@phil> Mime-Version: 1.0 Message-ID: <2019062409570947233513@rock-chips.com> Content-Type: multipart/alternative; boundary="----=_001_NextPart256882183164_=----" To: Heiko Stuebner Cc: "mark.rutland" , robh+dt , =?utf-8?B?5byg5b+X5p2w77yI5Yib5paw77yJ?= , "manivannan.sadhasivam" , linux-rockchip , linux-arm-kernel , linux-kernel , devicetree List-ID: This is a multi-part message in MIME format. ------=_001_NextPart256882183164_=---- Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 SGksIEtlaWtvIGFuZCBNYW5pdmFubmFuOg0KDQpTb3JyeSBsYXRlIHRvIHJlcGx5IHNpbmNlIEkg bWlzc2VkIHRoaXMgbWFpbCBhZnRlciBhIGxvbmcgbGVhdmUgdGltZS4NCg0KDQoNCmpheS54dUBy b2NrLWNoaXBzLmNvbQ0KIA0KRnJvbTogSGVpa28gU3R1ZWJuZXINCkRhdGU6IDIwMTktMDYtMTQg MTc6NTINClRvOiBKaWFucXVuIFh1DQpDQzogbWFyay5ydXRsYW5kOyByb2JoK2R0OyB6aGFuZ3pq OyBtYW5pdmFubmFuLnNhZGhhc2l2YW07IGxpbnV4LXJvY2tjaGlwOyBsaW51eC1hcm0ta2VybmVs OyBsaW51eC1rZXJuZWw7IGRldmljZXRyZWUNClN1YmplY3Q6IFJlOiBbUEFUQ0ggdjMgMS8xXSBh cm02NDogZHRzOiByb2NrY2hpcDogYWRkIGNvcmUgZHRzaSBmaWxlIGZvciBSSzMzOTlQcm8gU29D cw0KSGkgSmlhbnF1biwNCiANCkFtIERvbm5lcnN0YWcsIDMwLiBNYWkgMjAxOSwgMDI6MDg6NDgg Q0VTVCBzY2hyaWViIEppYW5xdW4gWHU6DQo+IFRoaXMgcGF0Y2ggYWRkcyBjb3JlIGR0c2kgZmls ZSBmb3IgUm9ja2NoaXAgUkszMzk5UHJvIFNvQ3MsDQo+IGluY2x1ZGUgcmszMzk5LmR0c2kuIEFs c28gZW5hYmxlIHBjaWVpMC9wY2llX3BoeSBmb3IgQVAgdG8NCj4gdGFsayB0byBOUFUgcGFydCBp bnNpZGUgU29DLg0KPiANCj4gU2lnbmVkLW9mZi1ieTogSmlhbnF1biBYdSA8amF5Lnh1QHJvY2st Y2hpcHMuY29tPg0KIA0KY291bGQgeW91IGFkZCB0aGUgbmVjZXNzYXJ5IHBpbmN0cmwgZW50cnks IGFzIHN1Z2dlc3RlZCBieSBNYW5pdmFubmFuPw0KSGksIHRoZXJlIGlzIG5vIHBpbmN0cmwgZm9y IGVwLWdwaW9zLCB3aGljaCB1c2VkIGFzIEdQSU8sIHRoZXkgd2lsbCBzZXQgYnkgZ3BpbyBkcml2 ZXINCm11eCB0byBHUElPIGRlZmF1bHRseS4NCiANClRoYW5rcw0KSGVpa28NCiANCj4gLS0tDQo+ IGNoYW5nZXMgc2luY2UgdjI6DQo+IC0gb25seSBlbmFibGUgcGNpZTAgYW5kIHBjaWVfcGh5IG5v ZGVzLCB0aGFua3MgZm9yIEhlaWtvIGFuZCBtYW5pdmFubmFuDQo+IA0KPiBjaGFuZ2VzIHNpbmNl IHYxOg0KPiAtIHJlbW92ZSBkZmkgYW5kIGRtYw0KPiANCj4gIGFyY2gvYXJtNjQvYm9vdC9kdHMv cm9ja2NoaXAvcmszMzk5cHJvLmR0c2kgfCAyMiArKysrKysrKysrKysrKysrKysrKysNCj4gIDEg ZmlsZSBjaGFuZ2VkLCAyMiBpbnNlcnRpb25zKCspDQo+ICBjcmVhdGUgbW9kZSAxMDA2NDQgYXJj aC9hcm02NC9ib290L2R0cy9yb2NrY2hpcC9yazMzOTlwcm8uZHRzaQ0KPiANCj4gZGlmZiAtLWdp dCBhL2FyY2gvYXJtNjQvYm9vdC9kdHMvcm9ja2NoaXAvcmszMzk5cHJvLmR0c2kgYi9hcmNoL2Fy bTY0L2Jvb3QvZHRzL3JvY2tjaGlwL3JrMzM5OXByby5kdHNpDQo+IG5ldyBmaWxlIG1vZGUgMTAw NjQ0DQo+IGluZGV4IDAwMDAwMDAwMDAwMC4uYmI1ZWJmNjYwOGI5DQo+IC0tLSAvZGV2L251bGwN Cj4gKysrIGIvYXJjaC9hcm02NC9ib290L2R0cy9yb2NrY2hpcC9yazMzOTlwcm8uZHRzaQ0KPiBA QCAtMCwwICsxLDIyIEBADQo+ICsvLyBTUERYLUxpY2Vuc2UtSWRlbnRpZmllcjogKEdQTC0yLjAr IE9SIE1JVCkNCj4gKy8vIENvcHlyaWdodCAoYykgMjAxOSBGdXpob3UgUm9ja2NoaXAgRWxlY3Ry b25pY3MgQ28uLCBMdGQuDQo+ICsNCj4gKyNpbmNsdWRlICJyazMzOTkuZHRzaSINCj4gKw0KPiAr LyB7DQo+ICsgY29tcGF0aWJsZSA9ICJyb2NrY2hpcCxyazMzOTlwcm8iOw0KPiArfTsNCj4gKw0K PiArLyogRGVmYXVsdCB0byBlbmFibGVkIHNpbmNlIEFQIHRhbGsgdG8gTlBVIHBhcnQgb3ZlciBw Y2llICovDQo+ICsmcGNpZV9waHkgew0KPiArIHN0YXR1cyA9ICJva2F5IjsNCj4gK307DQo+ICsN Cj4gKy8qIERlZmF1bHQgdG8gZW5hYmxlZCBzaW5jZSBBUCB0YWxrIHRvIE5QVSBwYXJ0IG92ZXIg cGNpZSAqLw0KPiArJnBjaWUwIHsNCj4gKyBlcC1ncGlvcyA9IDwmZ3BpbzAgUktfUEI0IEdQSU9f QUNUSVZFX0hJR0g+Ow0KPiArIG51bS1sYW5lcyA9IDw0PjsNCj4gKyBwaW5jdHJsLW5hbWVzID0g ImRlZmF1bHQiOw0KPiArIHBpbmN0cmwtMCA9IDwmcGNpZV9jbGtyZXFuX2NwbT47DQo+ICsgc3Rh dHVzID0gIm9rYXkiOw0KPiArfTsNCj4gDQogDQogDQogDQogDQogDQo= ------=_001_NextPart256882183164_=---- Content-Type: text/html; charset="utf-8" Content-Transfer-Encoding: quoted-printable =0A
Hi, Keiko and Manivann= an:

Sorry late to reply since I missed this mail = after a long leave time.
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<= div style=3D"MARGIN: 10px; FONT-FAMILY: verdana; FONT-SIZE: 10pt">
jay= .xu@rock-chips.com
=0A
 
Date: 2019-06-14 17:52
Subject: Re: [PA= TCH v3 1/1] arm64: dts: rockchip: add core dtsi file for RK3399Pro SoCs
Hi Jianqun,
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=0A
Am D= onnerstag, 30. Mai 2019, 02:08:48 CEST schrieb Jianqun Xu:
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&g= t; This patch adds core dtsi file for Rockchip RK3399Pro SoCs,
=0A> include rk3399.dtsi. Also enable pciei0/pcie_phy for AP to
=0A=
> talk to NPU part inside SoC.
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>
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>= ; Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
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&nb= sp;
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could you add the necessary pinctrl entry, as suggested b= y Manivannan?
Hi, there is no pinctrl for ep-gpios, which used a= s GPIO, they will set by gpio driver
mux to GPIO defaultly.=0A
 
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Thanks
=0A
Heiko
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 =
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> ---
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> changes since v2:
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&g= t; - only enable pcie0 and pcie_phy nodes, thanks for Heiko and manivannan=
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>
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> changes since v1:
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> = - remove dfi and dmc
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>
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>  arch/arm64= /boot/dts/rockchip/rk3399pro.dtsi | 22 +++++++++++++++++++++
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= >  1 file changed, 22 insertions(+)
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>  create= mode 100644 arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
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>=
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> diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro.dt= si b/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
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> new fil= e mode 100644
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> index 000000000000..bb5ebf6608b9
=0A<= div>> --- /dev/null
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> +++ b/arch/arm64/boot/dts/rockchi= p/rk3399pro.dtsi
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> @@ -0,0 +1,22 @@
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> +// = SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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> +// Copyright= (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
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> +
= =0A
> +#include "rk3399.dtsi"
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> +
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>= +/ {
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> + compatible =3D "rockchip,rk3399pro";
=0A> +};
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> +
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> +/* Default to enabled si= nce AP talk to NPU part over pcie */
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> +&pcie_phy {=0A
> + status =3D "okay";
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> +};
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&g= t; +
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> +/* Default to enabled since AP talk to NPU part ov= er pcie */
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> +&pcie0 {
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> + ep-gpios = =3D <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
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> + num-la= nes =3D <4>;
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> + pinctrl-names =3D "default";
= =0A
> + pinctrl-0 =3D <&pcie_clkreqn_cpm>;
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&= gt; + status =3D "okay";
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> +};
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>
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