From: Stephen Boyd <sboyd@kernel.org>
To: alexandre.belloni@bootlin.com, ludovic.desroches@microchip.com,
mark.rutland@arm.com, mturquette@baylibre.com,
nicolas.ferre@microchip.com, robh+dt@kernel.org
Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
Claudiu Beznea <claudiu.beznea@microchip.com>
Subject: Re: [PATCH v5 0/4] add slow clock support for SAM9X60
Date: Thu, 27 Jun 2019 07:57:37 -0700 [thread overview]
Message-ID: <20190627145738.42BD52086D@mail.kernel.org> (raw)
In-Reply-To: <1561646841-7663-1-git-send-email-claudiu.beznea@microchip.com>
Quoting Claudiu Beznea (2019-06-27 07:47:17)
> Hi,
>
> This series add slow clock support for SAM9X60. Apart from previous IPs, this
> one uses different offsets in control register for different functionalities.
> The series adapt current driver to work for all IPs using per IP
> configurations initialized at probe.
>
> Stephen,
>
> I send a new version of this since I'm not seeing the patches on clk-next
> and I though you may had issues with the previous version of this series.
Ok thanks. I see that you've fixed it to send plain text. Great! But I
already applied the other patches so I'll just keep what I had. Should
be pushed out to clk-next today.
prev parent reply other threads:[~2019-06-27 14:57 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-27 14:47 [PATCH v5 0/4] add slow clock support for SAM9X60 Claudiu Beznea
2019-06-27 14:47 ` [PATCH v5 1/4] clk: at91: sckc: sama5d4 has no bypass support Claudiu Beznea
2019-06-27 14:47 ` [PATCH v5 2/4] clk: at91: sckc: add support to specify registers bit offsets Claudiu Beznea
2019-06-27 14:47 ` [PATCH v5 3/4] dt-bindings: clk: at91: add bindings for SAM9X60's slow clock controller Claudiu Beznea
2019-06-27 14:47 ` [PATCH v5 4/4] clk: at91: sckc: add support for SAM9X60 Claudiu Beznea
2019-06-27 14:57 ` Stephen Boyd [this message]
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