From mboxrd@z Thu Jan 1 00:00:00 1970 From: Vinod Koul Subject: Re: [PATCH v5 0/6] add edma2 for i.mx7ulp Date: Wed, 3 Jul 2019 13:28:48 +0530 Message-ID: <20190703075848.GR2911@vkoul-mobl> References: <20190625094324.19196-1-yibin.gong@nxp.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: <20190625094324.19196-1-yibin.gong@nxp.com> Sender: linux-kernel-owner@vger.kernel.org To: yibin.gong@nxp.com Cc: robh@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, festevam@gmail.com, mark.rutland@arm.com, dan.j.williams@intel.com, angelo@sysam.it, linux-imx@nxp.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, devicetree@vger.kernel.org, kernel@pengutronix.de List-Id: devicetree@vger.kernel.org On 25-06-19, 17:43, yibin.gong@nxp.com wrote: > From: Robin Gong > > This patch set add new version of edma for i.mx7ulp, the main changes > are as belows: > 1. only one dmamux. > 2. another clock dma_clk except dmamux clk. > 3. 16 independent interrupts instead of only one interrupt for > all channels > For the first change, need modify fsl-edma-common.c and mcf-edma, > so create the first two patches to prepare without any function impact. > > For the third change, need request single irq for every channel with > the legacy handler. But actually 2 dma channels share one interrupt(16 > channel interrupts, but 32 channels.),ch0/ch16,ch1/ch17... For now, just > simply request irq without IRQF_SHARED flag, since 16 channels are enough > on i.mx7ulp whose M4 domain own some peripherals. Applied patches 1-5, thanks -- ~Vinod