From mboxrd@z Thu Jan 1 00:00:00 1970 From: Bjorn Andersson Subject: Re: [PATCH v3 07/14] clk: qcom: hfpll: register as clock provider Date: Thu, 11 Jul 2019 08:07:54 -0700 Message-ID: <20190711150754.GH7234@tuxbook-pro> References: <20190625164733.11091-1-jorge.ramirez-ortiz@linaro.org> <20190625164733.11091-8-jorge.ramirez-ortiz@linaro.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: <20190625164733.11091-8-jorge.ramirez-ortiz@linaro.org> Sender: linux-kernel-owner@vger.kernel.org To: Jorge Ramirez-Ortiz Cc: sboyd@kernel.org, david.brown@linaro.org, jassisinghbrar@gmail.com, mark.rutland@arm.com, mturquette@baylibre.com, robh+dt@kernel.org, will.deacon@arm.com, arnd@arndb.de, horms+renesas@verge.net.au, heiko@sntech.de, sibis@codeaurora.org, enric.balletbo@collabora.com, jagan@amarulasolutions.com, olof@lixom.net, vkoul@kernel.org, niklas.cassel@linaro.org, georgi.djakov@linaro.org, amit.kucheria@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-msm@vger.kernel.org, khasim.mohammed@linaro.org List-Id: devicetree@vger.kernel.org On Tue 25 Jun 09:47 PDT 2019, Jorge Ramirez-Ortiz wrote: > Make the output of the high frequency pll a clock provider. > On the QCS404 this PLL controls cpu frequency scaling. > > Co-developed-by: Niklas Cassel > Signed-off-by: Niklas Cassel > Signed-off-by: Jorge Ramirez-Ortiz > Acked-by: Stephen Boyd Reviewed-by: Bjorn Andersson > --- > drivers/clk/qcom/hfpll.c | 10 +++++++++- > 1 file changed, 9 insertions(+), 1 deletion(-) > > diff --git a/drivers/clk/qcom/hfpll.c b/drivers/clk/qcom/hfpll.c > index 87b7f46d27e0..0ffed0d41c50 100644 > --- a/drivers/clk/qcom/hfpll.c > +++ b/drivers/clk/qcom/hfpll.c > @@ -53,6 +53,7 @@ static int qcom_hfpll_probe(struct platform_device *pdev) > struct regmap *regmap; > struct clk_hfpll *h; > struct clk *pclk; > + int ret; > struct clk_init_data init = { > .parent_names = (const char *[]){ "xo" }, > .num_parents = 1, > @@ -87,7 +88,14 @@ static int qcom_hfpll_probe(struct platform_device *pdev) > h->clkr.hw.init = &init; > spin_lock_init(&h->lock); > > - return devm_clk_register_regmap(&pdev->dev, &h->clkr); > + ret = devm_clk_register_regmap(dev, &h->clkr); > + if (ret) { > + dev_err(dev, "failed to register regmap clock: %d\n", ret); > + return ret; > + } > + > + return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, > + &h->clkr.hw); > } > > static struct platform_driver qcom_hfpll_driver = { > -- > 2.21.0 >