From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rob Herring Subject: Re: [PATCH v2 07/11] dt-bindings: mmc: arasan: Add optional properties for Arasan SDHCI Date: Mon, 22 Jul 2019 16:01:34 -0600 Message-ID: <20190722220134.GA8281@bogus> References: <1561958991-21935-1-git-send-email-manish.narani@xilinx.com> <1561958991-21935-8-git-send-email-manish.narani@xilinx.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: <1561958991-21935-8-git-send-email-manish.narani@xilinx.com> Sender: linux-kernel-owner@vger.kernel.org To: Manish Narani Cc: ulf.hansson@linaro.org, mark.rutland@arm.com, heiko@sntech.de, michal.simek@xilinx.com, adrian.hunter@intel.com, christoph.muellner@theobroma-systems.com, philipp.tomsich@theobroma-systems.com, viresh.kumar@linaro.org, scott.branden@broadcom.com, ayaka@soulik.info, kernel@esmil.dk, tony.xie@rock-chips.com, rajan.vaja@xilinx.com, jolly.shah@xilinx.com, nava.manne@xilinx.com, mdf@kernel.org, olof@lixom.net, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org List-Id: devicetree@vger.kernel.org On Mon, Jul 01, 2019 at 10:59:47AM +0530, Manish Narani wrote: > Add optional propeties for Arasan SDHCI which are used to set clk delays > for different speed modes in the controller. > > Signed-off-by: Manish Narani > --- > Documentation/devicetree/bindings/mmc/arasan,sdhci.txt | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) > > diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt > index 7c79496..7425d52 100644 > --- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt > +++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt > @@ -49,6 +49,21 @@ Optional Properties: > properly. Test mode can be used to force the controller to function. > - xlnx,int-clock-stable-broken: when present, the controller always reports > that the internal clock is stable even when it is not. > + - clk-phase-legacy: Input/Output Clock Delay pair in degrees for Legacy Mode. > + - clk-phase-mmc-hs: Input/Output Clock Delay pair degrees for MMC HS. > + - clk-phase-sd-hs: Input/Output Clock Delay pair in degrees for SD HS. > + - clk-phase-uhs-sdr12: Input/Output Clock Delay pair in degrees for SDR12. > + - clk-phase-uhs-sdr25: Input/Output Clock Delay pair in degrees for SDR25. > + - clk-phase-uhs-sdr50: Input/Output Clock Delay pair in degrees for SDR50. > + - clk-phase-uhs-sdr104: Input/Output Clock Delay pair in degrees for SDR104. > + - clk-phase-uhs-ddr50: Input/Output Clock Delay pair in degrees for SD DDR50. > + - clk-phase-mmc-ddr52: Input/Output Clock Delay pair in degrees for MMC DDR52. > + - clk-phase-mmc-hs200: Input/Output Clock Delay pair in degrees for MMC HS200. > + - clk-phase-mmc-hs400: Input/Output Clock Delay pair in degrees for MMC HS400. Either these need vendor prefixes or be added as common properties if that makes sense. Rob > + > + Above mentioned are the clock (phase) delays which are to be configured in the > + controller while switching to particular speed mode. If not specified, driver > + will configure the default value defined for particular mode in it. > > Example: > sdhci@e0100000 { > -- > 2.1.1 >