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From: Maxime Ripard <maxime.ripard-LDxbnhwyfcJBDgjK7y7TUQ@public.gmane.org>
To: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	Linus Walleij
	<linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-gpio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org,
	Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
	Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>,
	linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Subject: Re: [PATCH v4 7/8] dt-bindings: arm: sunxi: add binding for Lichee Zero Plus core board
Date: Wed, 24 Jul 2019 16:14:25 +0200	[thread overview]
Message-ID: <20190724141425.aycdkdwlgmljwpgr@flea> (raw)
In-Reply-To: <7d24576697521f4985617113dbc4cc41-h8G6r0blFSE@public.gmane.org>

On Wed, Jul 24, 2019 at 09:09:01PM +0800, Icenowy Zheng wrote:
> 在 2019-07-23 03:29,Maxime Ripard 写道:
> > On Sat, Jul 20, 2019 at 07:39:08PM +0800, Icenowy Zheng wrote:
> > >
> > >
> > > 于 2019年7月20日 GMT+08:00 下午6:13:18, Maxime Ripard
> > > <maxime.ripard-LDxbnhwyfcJBDgjK7y7TUQ@public.gmane.org> 写到:
> > > >On Sat, Jul 13, 2019 at 11:46:33AM +0800, Icenowy Zheng wrote:
> > > >> The Lichee Zero Plus is a core board made by Sipeed, with a microUSB
> > > >> connector on it, TF slot or WSON8 SD chip, optional eMMC or SPI
> > > >Flash.
> > > >> It has a gold finger connector for expansion, and UART is available
> > > >from
> > > >> reserved pins w/ 2.54mm pitch. The board can use either SoChip S3 or
> > > >> Allwinner V3L SoCs.
> > > >>
> > > >> Add the device tree binding of the basic version of the core board --
> > > >> w/o eMMC or SPI Flash, w/ TF slot or WSON8 SD, and use S3 SoC.
> > > >>
> > > >> Signed-off-by: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
> > > >> ---
> > > >> No changes since v3.
> > > >>
> > > >> Patch introduced in v2.
> > > >>
> > > >>  Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++
> > > >>  1 file changed, 5 insertions(+)
> > > >>
> > > >> diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml
> > > >b/Documentation/devicetree/bindings/arm/sunxi.yaml
> > > >> index 000a00d12d6a..48c126a7a848 100644
> > > >> --- a/Documentation/devicetree/bindings/arm/sunxi.yaml
> > > >> +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml
> > > >> @@ -353,6 +353,11 @@ properties:
> > > >>            - const: licheepi,licheepi-zero
> > > >>            - const: allwinner,sun8i-v3s
> > > >>
> > > >> +      - description: Lichee Zero Plus (with S3, without eMMC/SPI
> > > >Flash)
> > > >> +        items:
> > > >> +          - const: sipeed,lichee-zero-plus
> > > >> +          - const: allwinner,sun8i-s3
> > > >
> > > >If the S3 is just a rebranded V3, then we should have the v3 compatile
> > > >in that list too.
> > >
> > > S3 is V3 with copackaged DDR3 DRAM.
> > >
> > > It's pin incompatible w/ V3.
> >
> > Does it matter though?
> >
> > If the only thing that changes is the package, we're not manipulating
> > that, and any software that deals with the v3 can deal with the
> > s3. Which is what the compatible is about.
>
> Okay. Should the S3 compatible be kept befoer the V3 one?

Yep, something like (in the DT)

compatible = "sipeed,lichee-zero-plus", "allwinner,sun8i-s3", "allwinner,sun8i-v3"

Maxime

--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

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  parent reply	other threads:[~2019-07-24 14:14 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-07-13  3:46 [PATCH v4 0/8] Support for Allwinner V3/S3L and Sochip S3 Icenowy Zheng
     [not found] ` <20190713034634.44585-1-icenowy-h8G6r0blFSE@public.gmane.org>
2019-07-13  3:46   ` [PATCH v4 1/8] pinctrl: sunxi: v3s: introduce support for V3 Icenowy Zheng
     [not found]     ` <20190713034634.44585-2-icenowy-h8G6r0blFSE@public.gmane.org>
2019-07-20  9:20       ` Maxime Ripard
2019-07-13  3:46   ` [PATCH v4 5/8] clk: sunxi-ng: v3s: add Allwinner V3 support Icenowy Zheng
2019-07-20  9:46     ` Maxime Ripard
     [not found]     ` <20190713034634.44585-6-icenowy-h8G6r0blFSE@public.gmane.org>
2019-07-22 17:07       ` Rob Herring
2019-07-13  3:46   ` [PATCH v4 6/8] ARM: sunxi: dts: s3/s3l/v3: add DTSI files for S3/S3L/V3 SoCs Icenowy Zheng
     [not found]     ` <20190713034634.44585-7-icenowy-h8G6r0blFSE@public.gmane.org>
2019-07-20  9:48       ` Maxime Ripard
2019-07-20  9:50         ` Icenowy Zheng
2019-07-13  3:46   ` [PATCH v4 7/8] dt-bindings: arm: sunxi: add binding for Lichee Zero Plus core board Icenowy Zheng
     [not found]     ` <20190713034634.44585-8-icenowy-h8G6r0blFSE@public.gmane.org>
2019-07-15 17:03       ` Rob Herring
2019-07-20 10:13       ` Maxime Ripard
2019-07-20 11:39         ` Icenowy Zheng
2019-07-22 19:29           ` Maxime Ripard
2019-07-24 13:09             ` Icenowy Zheng
     [not found]               ` <7d24576697521f4985617113dbc4cc41-h8G6r0blFSE@public.gmane.org>
2019-07-24 14:14                 ` Maxime Ripard [this message]
2019-07-13  3:46 ` [PATCH v4 2/8] clk: sunxi-ng: v3s: add the missing PLL_DDR1 Icenowy Zheng
     [not found]   ` <20190713034634.44585-3-icenowy-h8G6r0blFSE@public.gmane.org>
2019-07-20  9:43     ` Maxime Ripard
2019-07-13  3:46 ` [PATCH v4 3/8] dt-bindings: clk: sunxi-ccu: add compatible string for V3 CCU Icenowy Zheng
     [not found]   ` <20190713034634.44585-4-icenowy-h8G6r0blFSE@public.gmane.org>
2019-07-20  9:44     ` Maxime Ripard
2019-07-13  3:46 ` [PATCH v4 4/8] clk: sunxi-ng: v3s: add missing clock slices for MMC2 module clocks Icenowy Zheng
     [not found]   ` <20190713034634.44585-5-icenowy-h8G6r0blFSE@public.gmane.org>
2019-07-20  9:44     ` Maxime Ripard
2019-07-20  9:45       ` Icenowy Zheng
2019-07-13  3:46 ` [PATCH v4 8/8] ARM: dts: sun8i: s3: add devicetree for Lichee zero plus w/ S3 Icenowy Zheng
     [not found]   ` <20190713034634.44585-9-icenowy-h8G6r0blFSE@public.gmane.org>
2019-07-20 10:12     ` Maxime Ripard

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