From mboxrd@z Thu Jan 1 00:00:00 1970 From: Niklas Cassel Subject: [PATCH v2 04/14] dt-bindings: cpufreq: qcom-nvmem: Make speedbin related properties optional Date: Thu, 25 Jul 2019 12:41:32 +0200 Message-ID: <20190725104144.22924-5-niklas.cassel@linaro.org> References: <20190725104144.22924-1-niklas.cassel@linaro.org> Mime-Version: 1.0 Content-Transfer-Encoding: 8bit Return-path: In-Reply-To: <20190725104144.22924-1-niklas.cassel@linaro.org> Sender: linux-kernel-owner@vger.kernel.org To: Andy Gross , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd Cc: linux-arm-msm@vger.kernel.org, jorge.ramirez-ortiz@linaro.org, bjorn.andersson@linaro.org, ulf.hansson@linaro.org, Niklas Cassel , Rob Herring , Rob Herring , Mark Rutland , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org List-Id: devicetree@vger.kernel.org Not all Qualcomm platforms need to care about the speedbin efuse, nor the value blown into the speedbin efuse. Therefore, make the nvmem-cells and opp-supported-hw properties optional. Signed-off-by: Niklas Cassel Reviewed-by: Ilia Lin Reviewed-by: Rob Herring --- Changes since V1: -Picked up tags. Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt index 198441e80ba8..c5ea8b90e35d 100644 --- a/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt +++ b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt @@ -20,6 +20,10 @@ In 'cpus' nodes: In 'operating-points-v2' table: - compatible: Should be - 'operating-points-v2-kryo-cpu' for apq8096 and msm8996. + +Optional properties: +-------------------- +In 'operating-points-v2' table: - nvmem-cells: A phandle pointing to a nvmem-cells node representing the efuse registers that has information about the speedbin that is used to select the right frequency/voltage -- 2.21.0