From mboxrd@z Thu Jan 1 00:00:00 1970 From: Philippe Schenker Subject: [PATCH 07/22] ARM: dts: imx7-colibri: fix 1.8V/UHS support Date: Tue, 30 Jul 2019 16:46:34 +0200 Message-ID: <20190730144649.19022-8-dev@pschenker.ch> References: <20190730144649.19022-1-dev@pschenker.ch> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20190730144649.19022-1-dev@pschenker.ch> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: marcel.ziswiler@toradex.com, max.krummenacher@toradex.com, stefan@agner.ch, devicetree@vger.kernel.org, Rob Herring , Shawn Guo , Mark Rutland Cc: Stefan Agner , Sascha Hauer , linux-kernel@vger.kernel.org, Philippe Schenker , NXP Linux Team , Pengutronix Kernel Team , Fabio Estevam , linux-arm-kernel@lists.infradead.org List-Id: devicetree@vger.kernel.org From: Stefan Agner Add pinmuxing and do not specify voltage restrictions in the module level device tree. Signed-off-by: Stefan Agner Signed-off-by: Philippe Schenker --- arch/arm/boot/dts/imx7-colibri.dtsi | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx7-colibri.dtsi b/arch/arm/boot/dts/imx7-colibri.dtsi index 16d1a1ed1aff..67f5e0c87fdc 100644 --- a/arch/arm/boot/dts/imx7-colibri.dtsi +++ b/arch/arm/boot/dts/imx7-colibri.dtsi @@ -326,7 +326,6 @@ &usdhc1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_cd_usdhc1>; - no-1-8-v; cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; disable-wp; vqmmc-supply = <®_LDO2>; @@ -671,6 +670,28 @@ >; }; + pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x5a + MX7D_PAD_SD1_CLK__SD1_CLK 0x1a + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x5b + MX7D_PAD_SD1_CLK__SD1_CLK 0x1b + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b + >; + }; + pinctrl_usdhc3: usdhc3grp { fsl,pins = < MX7D_PAD_SD3_CMD__SD3_CMD 0x59 -- 2.22.0