From mboxrd@z Thu Jan 1 00:00:00 1970 From: Philippe Schenker Subject: [PATCH v2 07/20] ARM: dts: imx7-colibri: fix 1.8V/UHS support Date: Wed, 31 Jul 2019 12:38:12 +0000 Message-ID: <20190731123750.25670-8-philippe.schenker@toradex.com> References: <20190731123750.25670-1-philippe.schenker@toradex.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-2" Content-Transfer-Encoding: quoted-printable Return-path: In-Reply-To: <20190731123750.25670-1-philippe.schenker@toradex.com> Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org To: Marcel Ziswiler , Max Krummenacher , "stefan@agner.ch" , "devicetree@vger.kernel.org" , Rob Herring , Shawn Guo , Mark Rutland , =?iso-8859-2?Q?Michal_Vok=E1=E8?= , Fabio Estevam Cc: Stefan Agner , Philippe Schenker , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , Pengutronix Kernel Team , NXP Linux Team , Sascha Hauer List-Id: devicetree@vger.kernel.org From: Stefan Agner Add pinmuxing and do not specify voltage restrictions in the module level device tree. Signed-off-by: Stefan Agner Signed-off-by: Philippe Schenker --- Changes in v2: None arch/arm/boot/dts/imx7-colibri.dtsi | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx7-colibri.dtsi b/arch/arm/boot/dts/imx7-c= olibri.dtsi index 16d1a1ed1aff..67f5e0c87fdc 100644 --- a/arch/arm/boot/dts/imx7-colibri.dtsi +++ b/arch/arm/boot/dts/imx7-colibri.dtsi @@ -326,7 +326,6 @@ &usdhc1 { pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_usdhc1 &pinctrl_cd_usdhc1>; - no-1-8-v; cd-gpios =3D <&gpio1 0 GPIO_ACTIVE_LOW>; disable-wp; vqmmc-supply =3D <®_LDO2>; @@ -671,6 +670,28 @@ >; }; =20 + pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { + fsl,pins =3D < + MX7D_PAD_SD1_CMD__SD1_CMD 0x5a + MX7D_PAD_SD1_CLK__SD1_CLK 0x1a + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { + fsl,pins =3D < + MX7D_PAD_SD1_CMD__SD1_CMD 0x5b + MX7D_PAD_SD1_CLK__SD1_CLK 0x1b + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b + >; + }; + pinctrl_usdhc3: usdhc3grp { fsl,pins =3D < MX7D_PAD_SD3_CMD__SD3_CMD 0x59 --=20 2.22.0