From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from relay3-d.mail.gandi.net ([217.70.183.195]:59735 "EHLO relay3-d.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727230AbfHEKDQ (ORCPT ); Mon, 5 Aug 2019 06:03:16 -0400 From: Miquel Raynal Subject: [PATCH 0/8] AP807 clocks support Date: Mon, 5 Aug 2019 12:03:02 +0200 Message-Id: <20190805100310.29048-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: devicetree-owner@vger.kernel.org To: Rob Herring , Mark Rutland , Michael Turquette , Stephen Boyd Cc: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, Thomas Petazzoni , Gregory Clement , Antoine Tenart , Maxime Chevallier , Nadav Haklai , Grzegorz Jaszczyk , Marcin Wojtas , Stefan Chulski , Yan Markman , Miquel Raynal List-ID: Hello, This is the first batch of changes (out of three) to support the brand new Marvell CN9130 SoCs which are made of one AP807 and one CP115. This clock series applies on top of Gregory's "AP806 CPU clocks" [1]. [1] https://patchwork.kernel.org/cover/11038577/ Thanks, Miquèl Ben Peled (3): clk: mvebu: ap80x-cpu: add AP807 CPU clock support clk: mvebu: ap806: Prepare the introduction of AP807 clock support clk: mvebu: ap80x: add AP807 clock support Christine Gharzuzi (1): clk: mvebu: ap806-cpu: prepare mapping of AP807 CPU clock Miquel Raynal (3): dt-bindings: ap80x: Document AP807 CPU clock compatible dt-bindings: ap806: Document AP807 clock compatible clk: mvebu: ap806: be more explicit on what SaR is Omri Itach (1): clk: mvebu: ap806: add AP-DCLK (hclk) to system controller driver .../arm/marvell/ap806-system-controller.txt | 17 +- drivers/clk/mvebu/ap-cpu-clk.c | 139 ++++++++++++--- drivers/clk/mvebu/ap806-system-controller.c | 162 ++++++++++++++---- 3 files changed, 253 insertions(+), 65 deletions(-) -- 2.20.1