From mboxrd@z Thu Jan 1 00:00:00 1970 From: Philippe Schenker Subject: [PATCH v4 14/21] ARM: dts: imx6ull-colibri: Add sleep mode to fec Date: Mon, 12 Aug 2019 14:21:36 +0000 Message-ID: <20190812142105.1995-15-philippe.schenker@toradex.com> References: <20190812142105.1995-1-philippe.schenker@toradex.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-2" Content-Transfer-Encoding: quoted-printable Return-path: In-Reply-To: <20190812142105.1995-1-philippe.schenker@toradex.com> Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org To: Marcel Ziswiler , Max Krummenacher , "stefan@agner.ch" , "devicetree@vger.kernel.org" , Rob Herring , Shawn Guo , Mark Rutland , =?iso-8859-2?Q?Michal_Vok=E1=E8?= , Fabio Estevam Cc: Philippe Schenker , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , Pengutronix Kernel Team , NXP Linux Team , Sascha Hauer List-Id: devicetree@vger.kernel.org Do not change the clock as the power for this phy is switched with that clock. Signed-off-by: Philippe Schenker Acked-by: Marcel Ziswiler --- Changes in v4: - Add Marcel Ziswiler's Ack Changes in v3: None Changes in v2: None arch/arm/boot/dts/imx6ull-colibri.dtsi | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx= 6ull-colibri.dtsi index d56728f03c35..1019ce69a242 100644 --- a/arch/arm/boot/dts/imx6ull-colibri.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi @@ -62,8 +62,9 @@ }; =20 &fec2 { - pinctrl-names =3D "default"; + pinctrl-names =3D "default", "sleep"; pinctrl-0 =3D <&pinctrl_enet2>; + pinctrl-1 =3D <&pinctrl_enet2_sleep>; phy-mode =3D "rmii"; phy-handle =3D <ðphy1>; status =3D "okay"; @@ -220,6 +221,21 @@ >; }; =20 + pinctrl_enet2_sleep: enet2sleepgrp { + fsl,pins =3D < + MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x0 + MX6UL_PAD_GPIO1_IO07__GPIO1_IO07 0x0 + MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x0 + MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x0 + MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x0 + MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 + MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x0 + MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x0 + MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x0 + >; + }; + pinctrl_ecspi1_cs: ecspi1-cs-grp { fsl,pins =3D < MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x000a0 --=20 2.22.0