From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Z.q. Hou" Subject: [PATCHv8 3/7] dt-bindings: PCI: Add NXP Layerscape SoCs PCIe Gen4 controller Date: Tue, 13 Aug 2019 11:04:11 +0000 Message-ID: <20190813110557.45643-4-Zhiqiang.Hou@nxp.com> References: <20190813110557.45643-1-Zhiqiang.Hou@nxp.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: In-Reply-To: <20190813110557.45643-1-Zhiqiang.Hou@nxp.com> Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org To: "linux-pci@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "bhelgaas@google.com" , "robh+dt@kernel.org" , "arnd@arndb.de" , "mark.rutland@arm.com" , "l.subrahmanya@mobiveil.co.in" , "shawnguo@kernel.org" , "m.karthikeyan@mobiveil.co.in" , Leo Li , "lorenzo.pieralisi@arm.com" , "catalin.marinas@arm.com" , "will.deacon@arm.com" Cc: Mingkai Hu , "M.h. Lian" , Xiaowei Bao , "Z.q. Hou" List-Id: devicetree@vger.kernel.org From: Hou Zhiqiang Add PCIe Gen4 controller DT bindings of NXP Layerscape SoCs. Signed-off-by: Hou Zhiqiang Reviewed-by: Rob Herring --- V8: - No change. .../bindings/pci/layerscape-pcie-gen4.txt | 52 +++++++++++++++++++ MAINTAINERS | 8 +++ 2 files changed, 60 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/layerscape-pcie-g= en4.txt diff --git a/Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt= b/Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt new file mode 100644 index 000000000000..b40fb5d15d3d --- /dev/null +++ b/Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt @@ -0,0 +1,52 @@ +NXP Layerscape PCIe Gen4 controller + +This PCIe controller is based on the Mobiveil PCIe IP and thus inherits al= l +the common properties defined in mobiveil-pcie.txt. + +Required properties: +- compatible: should contain the platform identifier such as: + "fsl,lx2160a-pcie" +- reg: base addresses and lengths of the PCIe controller register blocks. + "csr_axi_slave": Bridge config registers + "config_axi_slave": PCIe controller registers +- interrupts: A list of interrupt outputs of the controller. Must contain = an + entry for each entry in the interrupt-names property. +- interrupt-names: It could include the following entries: + "intr": The interrupt that is asserted for controller interrupts + "aer": Asserted for aer interrupt when chip support the aer interrupt wi= th + none MSI/MSI-X/INTx mode,but there is interrupt line for aer. + "pme": Asserted for pme interrupt when chip support the pme interrupt wi= th + none MSI/MSI-X/INTx mode,but there is interrupt line for pme. +- dma-coherent: Indicates that the hardware IP block can ensure the cohere= ncy + of the data transferred from/to the IP block. This can avoid the softwar= e + cache flush/invalid actions, and improve the performance significantly. +- msi-parent : See the generic MSI binding described in + Documentation/devicetree/bindings/interrupt-controller/msi.txt. + +Example: + + pcie@3400000 { + compatible =3D "fsl,lx2160a-pcie"; + reg =3D <0x00 0x03400000 0x0 0x00100000 /* controller registers */ + 0x80 0x00000000 0x0 0x00001000>; /* configuration space */ + reg-names =3D "csr_axi_slave", "config_axi_slave"; + interrupts =3D , /* AER interrupt */ + , /* PME interrupt */ + ; /* controller interrupt */ + interrupt-names =3D "aer", "pme", "intr"; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + apio-wins =3D <8>; + ppio-wins =3D <8>; + dma-coherent; + bus-range =3D <0x0 0xff>; + msi-parent =3D <&its>; + ranges =3D <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 0d88e0d3960b..f9c1153ef60a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12324,6 +12324,14 @@ L: linux-arm-kernel@lists.infradead.org S: Maintained F: drivers/pci/controller/dwc/*layerscape* =20 +PCI DRIVER FOR NXP LAYERSCAPE GEN4 CONTROLLER +M: Hou Zhiqiang +L: linux-pci@vger.kernel.org +L: linux-arm-kernel@lists.infradead.org +S: Maintained +F: Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt +F: drivers/pci/controller/mobibeil/pcie-layerscape-gen4.c + PCI DRIVER FOR GENERIC OF HOSTS M: Will Deacon L: linux-pci@vger.kernel.org --=20 2.17.1