From mboxrd@z Thu Jan 1 00:00:00 1970 From: Brian Masney Subject: Re: [PATCH 09/11] ARM: dts: qcom: pm8941: add 5vs2 regulator node Date: Thu, 15 Aug 2019 18:44:17 -0400 Message-ID: <20190815224417.GA32072@onstation.org> References: <20190815004854.19860-1-masneyb@onstation.org> <20190815004854.19860-10-masneyb@onstation.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: Sender: linux-kernel-owner@vger.kernel.org To: Linus Walleij Cc: Bjorn Andersson , Rob Herring , Andy Gross , Andrzej Hajda , Neil Armstrong , Rob Clark , Sean Paul , Dave Airlie , Daniel Vetter , Mark Rutland , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Enric Balletbo i Serra , "open list:DRM PANEL DRIVERS" , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , "linux-kernel@vger.kernel.org" M List-Id: devicetree@vger.kernel.org On Thu, Aug 15, 2019 at 10:34:17AM +0200, Linus Walleij wrote: > On Thu, Aug 15, 2019 at 2:49 AM Brian Masney wrote: > > > pm8941 is missing the 5vs2 regulator node so let's add it since its > > needed to get the external display working. This regulator was already > > configured in the interrupts property on the parent node. > > > > Note that this regulator is referred to as mvs2 in the downstream MSM > > kernel sources. > > When I looked at it it seemed like this convention is used for power > supplies that appear on both the main PMIC and the "extra (boot? basic? > low power?) PMIC that the main 80xx PMIC has mvs1 and the > other 89xx PMIC has mvs2. According to the downstream MSM sources, the 5vs1 and 5vs2 rails are both on the second pm8941 PMIC: https://github.com/AICP/kernel_lge_hammerhead/blob/n7.1/arch/arm/boot/dts/msm8974-regulator.dtsi#L18 > I suppose it is named "mvs" on both PMICs and this is just a rail > name so as not to confuse the schematic? That sounds reasonable. > > Signed-off-by: Brian Masney > > Reviewed-by: Linus Walleij Thank you! Brian