From mboxrd@z Thu Jan 1 00:00:00 1970 From: jassisinghbrar@gmail.com Subject: [PATCH v2 1/2] dt-bindings: milbeaut-m10v-hdmac: Add Socionext Milbeaut HDMAC bindings Date: Sun, 18 Aug 2019 00:17:54 -0500 Message-ID: <20190818051754.17548-1-jassisinghbrar@gmail.com> References: <20190818051647.17475-1-jassisinghbrar@gmail.com> Return-path: In-Reply-To: <20190818051647.17475-1-jassisinghbrar@gmail.com> Sender: linux-kernel-owner@vger.kernel.org To: dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: vkoul@kernel.org, robh+dt@kernel.org, Jassi Brar List-Id: devicetree@vger.kernel.org From: Jassi Brar Document the devicetree bindings for Socionext Milbeaut HDMAC controller. Controller has upto 8 floating channels, that need a predefined slave-id to work from a set of slaves. Signed-off-by: Jassi Brar --- .../bindings/dma/milbeaut-m10v-hdmac.txt | 32 +++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/milbeaut-m10v-hdmac.txt diff --git a/Documentation/devicetree/bindings/dma/milbeaut-m10v-hdmac.txt b/Documentation/devicetree/bindings/dma/milbeaut-m10v-hdmac.txt new file mode 100644 index 000000000000..f0960724f1c7 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/milbeaut-m10v-hdmac.txt @@ -0,0 +1,32 @@ +* Milbeaut AHB DMA Controller + +Milbeaut AHB DMA controller has transfer capability bellow. + - device to memory transfer + - memory to device transfer + +Required property: +- compatible: Should be "socionext,milbeaut-m10v-hdmac" +- reg: Should contain DMA registers location and length. +- interrupts: Should contain all of the per-channel DMA interrupts. + Number of channels is configurable - 2, 4 or 8, so + the number of interrupts specfied should be {2,4,8}. +- #dma-cells: Should be 1. Specify the ID of the slave. +- clocks: Phandle to the clock used by the HDMAC module. + + +Example: + + hdmac1: dma-controller@1e110000 { + compatible = "socionext,milbeaut-m10v-hdmac"; + reg = <0x1e110000 0x10000>; + interrupts = <0 132 4>, + <0 133 4>, + <0 134 4>, + <0 135 4>, + <0 136 4>, + <0 137 4>, + <0 138 4>, + <0 139 4>; + #dma-cells = <1>; + clocks = <&dummy_clk>; + }; -- 2.17.1