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From: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
To: Brian Masney <masneyb-1iNe0GrtECGEi8DpZVb4nw@public.gmane.org>
Cc: mark.rutland-5wv7dgnIgG8@public.gmane.org,
	freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org,
	jcrouse-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org,
	jonathan-eSc4qw6YbEQ@public.gmane.org,
	devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	airlied-cv59FeDIM0c@public.gmane.org,
	linux-arm-msm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org,
	bjorn.andersson-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org,
	robdclark-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
	agross-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
	daniel-/w4YWyX8dFk@public.gmane.org,
	sean-p7yTbzM4H96eqtR555YLDQ@public.gmane.org
Subject: Re: [PATCH v5 2/7] dt-bindings: display: msm: gmu: add optional ocmem property
Date: Wed, 21 Aug 2019 14:26:02 -0500	[thread overview]
Message-ID: <20190821192602.GA16243@bogus> (raw)
In-Reply-To: <20190806002229.8304-3-masneyb-1iNe0GrtECGEi8DpZVb4nw@public.gmane.org>

On Mon, Aug 05, 2019 at 08:22:24PM -0400, Brian Masney wrote:
> Some A3xx and A4xx Adreno GPUs do not have GMEM inside the GPU core and
> must use the On Chip MEMory (OCMEM) in order to be functional. Add the
> optional ocmem property to the Adreno Graphics Management Unit bindings.
> 
> Signed-off-by: Brian Masney <masneyb@onstation.org>
> ---
> Changes since v4:
> - None
> 
> Changes since v3:
> - correct link to qcom,ocmem.yaml
> 
> Changes since v2:
> - Add a3xx example with OCMEM
> 
> Changes since v1:
> - None
> 
>  .../devicetree/bindings/display/msm/gmu.txt   | 50 +++++++++++++++++++
>  1 file changed, 50 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/display/msm/gmu.txt b/Documentation/devicetree/bindings/display/msm/gmu.txt
> index 90af5b0a56a9..672d557caba4 100644
> --- a/Documentation/devicetree/bindings/display/msm/gmu.txt
> +++ b/Documentation/devicetree/bindings/display/msm/gmu.txt
> @@ -31,6 +31,10 @@ Required properties:
>  - iommus: phandle to the adreno iommu
>  - operating-points-v2: phandle to the OPP operating points
>  
> +Optional properties:
> +- ocmem: phandle to the On Chip Memory (OCMEM) that's present on some Snapdragon
> +         SoCs. See Documentation/devicetree/bindings/sram/qcom,ocmem.yaml.

Sigh, to repeat my comment on v1 and v3:

We already have a couple of similar properties. Lets standardize on
'sram' as that is what TI already uses.

Rob
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  parent reply	other threads:[~2019-08-21 19:26 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-06  0:22 [PATCH v5 0/7] qcom: add OCMEM support Brian Masney
     [not found] ` <20190806002229.8304-1-masneyb-1iNe0GrtECGEi8DpZVb4nw@public.gmane.org>
2019-08-06  0:22   ` [PATCH v5 1/7] dt-bindings: soc: qcom: add On Chip MEMory (OCMEM) bindings Brian Masney
2019-08-06  0:22   ` [PATCH v5 2/7] dt-bindings: display: msm: gmu: add optional ocmem property Brian Masney
     [not found]     ` <20190806002229.8304-3-masneyb-1iNe0GrtECGEi8DpZVb4nw@public.gmane.org>
2019-08-21 19:26       ` Rob Herring [this message]
2019-08-21 19:38         ` Brian Masney
2019-08-06  0:22   ` [PATCH v5 3/7] firmware: qcom: scm: add OCMEM lock/unlock interface Brian Masney
2019-08-06  0:22   ` [PATCH v5 4/7] firmware: qcom: scm: add support to restore secure config to qcm_scm-32 Brian Masney
2019-08-06  0:22   ` [PATCH v5 5/7] soc: qcom: add OCMEM driver Brian Masney
2019-08-06  0:22   ` [PATCH v5 6/7] drm/msm/gpu: add ocmem init/cleanup functions Brian Masney
2019-08-06  0:22   ` [PATCH v5 7/7] ARM: qcom_defconfig: add ocmem support Brian Masney

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