[PATCH mvebu-dt64 0/3] Add Turris Mox device-tree

[PATCH mvebu-dt64 0/3] Add Turris Mox device-tree

[Marek Behún]

Hello,
this patch series adds device-tree for Turris Mox.

All the devices described in this device-tree are supported, although
the moxtet bus driver and moxtet GPIO driver are now only in
soc/for-next.

The device-tree includes <dt-bindings/bus/moxtet.h>. This file is not
present in mvebu/dt64, but is in soc/for-next.

I have addressed the issues Rob Herring had with this device-tree when
I sent a RFC in November 2018. These include:
 - since there are whole hierarchy of nodes that may be disabled since
   the modules are not connected, U-Boot removes these nodes
 - the documentation for board compatible flag was moved into
   armada-37xx dt-bindings documentation
 - reset_button was renamed to reset
 - reset-gpio was renamed to reset-gpios
 - flash partitions nodes are now contained in one 'partitions' node
 - moxtet node now has a driver in soc/for-next and has documented
   dt-bindings
Not addressed:
 - the switch nodes have names:
     switch0@10   switch1@11   switch2@12
     switch0@2    switch1@2    switch2@2
   Rob said that 'Ideally, we shouldn't have this switch0, switch1,
   etc.'
   The problem here is that the 4-port switch is always on the same MDIO
   address (0x2), but depending on it's position in this module topology
   it has different settings. Therefore we have three nodes, and only
   one of them can be ever enabled (only one 4-port switch can be
   connected). Since I did not change this for the 4-port switch, I left
   this naming also for 8-port switch.
   Hopefully this is not a major problem.
There were also other changes since the RFC, since there are new drivers
now in the kernel (for example the comphy driver for Armada 37xx).

Marek

Marek Behún (3):
  arm64: dts: marvell: armada-37xx: add SPI CS1 pinctrl
  dt-bindings: marvell: document Turris Mox compatible
  arm64: dts: marvell: add DTS for Turris Mox

 .../bindings/arm/marvell/armada-37xx.txt      |   8 +
 arch/arm64/boot/dts/marvell/Makefile          |   1 +
 .../dts/marvell/armada-3720-turris-mox.dts    | 841 ++++++++++++++++++
 arch/arm64/boot/dts/marvell/armada-37xx.dtsi  |   5 +
 4 files changed, 855 insertions(+)
 create mode 100644 arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts

-- 
2.21.0

[PATCH mvebu-dt64 1/3] arm64: dts: marvell: armada-37xx: add SPI CS1 pinctrl

[Marek Behún]

This adds pinctrl node for the GPIO to be used as SPI chip select 1.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Cc: Gregory CLEMENT <gregory.clement@bootlin.com>
---
 arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
index f43c43168b00..10812a556829 100644
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
@@ -215,6 +215,11 @@
 					function = "spi";
 				};
 
+				spi_cs1_pins: spi-cs1-pins {
+					groups = "spi_cs1";
+					function = "spi";
+				};
+
 				i2c1_pins: i2c1-pins {
 					groups = "i2c1";
 					function = "i2c";
-- 
2.21.0

[PATCH mvebu-dt64 2/3] dt-bindings: marvell: document Turris Mox compatible

[Marek Behún]

This adds the documentation for the Turris Mox compatible in armada-37xx
device-tree binding documentation.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Cc: Gregory CLEMENT <gregory.clement@bootlin.com>
Cc: Rob Herring <robh@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
---
 .../devicetree/bindings/arm/marvell/armada-37xx.txt       | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-37xx.txt b/Documentation/devicetree/bindings/arm/marvell/armada-37xx.txt
index eddde4faef01..f6d6642d81c0 100644
--- a/Documentation/devicetree/bindings/arm/marvell/armada-37xx.txt
+++ b/Documentation/devicetree/bindings/arm/marvell/armada-37xx.txt
@@ -48,3 +48,11 @@ avs: avs@11500 {
 	compatible = "marvell,armada-3700-avs", "syscon";
 	reg = <0x11500 0x40>;
 }
+
+
+CZ.NIC's Turris Mox SOHO router Device Tree Bindings
+----------------------------------------------------
+
+Required root node property:
+
+ - compatible: must contain "cznic,turris-mox"
-- 
2.21.0

[PATCH mvebu-dt64 3/3] arm64: dts: marvell: add DTS for Turris Mox

[Marek Behún]

This adds support for the Turris Mox board from CZ.NIC.

Turris Mox is as modular router based on the Armada 3720 SOC (same as
EspressoBin).

The basic board can be extended by different modules.
If those are connected, U-Boot lets the kernel know via device-tree.

Since modules can be connected in different order and some modules can
be connected multiple times (up to three modules containing 8-port
ethernet switch in DSA configuration can be connected) we decided
against using device-tree overlays, because it got complicated rather
quickly. (For example the SFP module can be connected directly to the
CPU, or after a switch module. There are four cases and all would need
different SFP overlay. There are two types of switch modules (8-port
with pass-through and 4-port with no pass-through). For those we would
again need at least 6 more overlays.)

We therefore decided to put all the possibly connected devices in one
device-tree and disable them by default. When U-Boot finds out which
modules are connected, it fixes the loaded device-tree accordingly just
before boot. By Rob Herring's suggestion we also made it so that U-Boot
completely removes nodes which are disabled after this fixup.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Cc: Rob Herring <robh@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: Gregory CLEMENT <gregory.clement@bootlin.com>
---
 arch/arm64/boot/dts/marvell/Makefile          |   1 +
 .../dts/marvell/armada-3720-turris-mox.dts    | 841 ++++++++++++++++++
 2 files changed, 842 insertions(+)
 create mode 100644 arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts

diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile
index caed4334f27d..243338c914a4 100644
--- a/arch/arm64/boot/dts/marvell/Makefile
+++ b/arch/arm64/boot/dts/marvell/Makefile
@@ -2,6 +2,7 @@
 # Mvebu SoC Family
 dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-db.dtb
 dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-espressobin.dtb
+dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-turris-mox.dtb
 dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-uDPU.dtb
 dtb-$(CONFIG_ARCH_MVEBU) += armada-7040-db.dtb
 dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-clearfog-gt-8k.dtb
diff --git a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts
new file mode 100644
index 000000000000..32ed2bbdab27
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts
@@ -0,0 +1,841 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree file for CZ.NIC Turris Mox Board
+ * 2019 by Marek Behun <marek.behun@nic.cz>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/bus/moxtet.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include "armada-372x.dtsi"
+
+/ {
+	model = "CZ.NIC Turris Mox Board";
+	compatible = "cznic,turris-mox", "marvell,armada3720",
+		     "marvell,armada3710";
+
+	aliases {
+		spi0 = &spi0;
+		ethernet1 = &eth1;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		red {
+			gpios = <&gpiosb 21 GPIO_ACTIVE_LOW>;
+			linux,default-trigger = "default-on";
+		};
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		reset {
+			label = "reset";
+			linux,code = <BTN_MISC>;
+			gpios = <&gpiosb 20 GPIO_ACTIVE_LOW>;
+			debounce-interval = <60>;
+		};
+	};
+
+	exp_usb3_vbus: usb3-vbus {
+		compatible = "regulator-fixed";
+		regulator-name = "usb3-vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+		regulator-always-on;
+		gpio = <&gpiosb 0 GPIO_ACTIVE_HIGH>;
+	};
+
+	usb3_phy: usb3-phy {
+		compatible = "usb-nop-xceiv";
+		vcc-supply = <&exp_usb3_vbus>;
+	};
+
+	vsdc_reg: vsdc-reg {
+		compatible = "regulator-gpio";
+		regulator-name = "vsdc";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+
+		gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>;
+		gpios-states = <0>;
+		states = <1800000 0x1
+			  3300000 0x0>;
+		enable-active-high;
+	};
+
+	vsdio_reg: vsdio-reg {
+		compatible = "regulator-gpio";
+		regulator-name = "vsdio";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+
+		gpios = <&gpiosb 22 GPIO_ACTIVE_HIGH>;
+		gpios-states = <0>;
+		states = <1800000 0x1
+			  3300000 0x0>;
+		enable-active-high;
+	};
+
+	sdhci1_pwrseq: sdhci1-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		reset-gpios = <&gpionb 19 GPIO_ACTIVE_HIGH>;
+		status = "okay";
+	};
+
+	sfp: sfp {
+		compatible = "sff,sfp+";
+		i2c-bus = <&i2c0>;
+		los-gpio = <&moxtet_sfp 0 GPIO_ACTIVE_HIGH>;
+		tx-fault-gpio = <&moxtet_sfp 1 GPIO_ACTIVE_HIGH>;
+		mod-def0-gpio = <&moxtet_sfp 2 GPIO_ACTIVE_LOW>;
+		tx-disable-gpio = <&moxtet_sfp 4 GPIO_ACTIVE_HIGH>;
+		rate-select0-gpio = <&moxtet_sfp 5 GPIO_ACTIVE_HIGH>;
+
+		/* enabled by U-Boot if SFP module is present */
+		status = "disabled";
+	};
+};
+
+&i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c1_pins>;
+	status = "okay";
+
+	rtc@6f {
+		compatible = "microchip,mcp7940x";
+		reg = <0x6f>;
+	};
+};
+
+&pcie_reset_pins {
+	function = "gpio";
+};
+
+&pcie0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
+	status = "okay";
+	max-link-speed = <2>;
+	reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
+	phys = <&comphy1 0>;
+
+	/* enabled by U-Boot if PCIe module is present */
+	status = "disabled";
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&eth0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&rgmii_pins>;
+	phy-mode = "rgmii-id";
+	phy = <&phy1>;
+	status = "okay";
+};
+
+&eth1 {
+	phy-mode = "2500base-x";
+	managed = "in-band-status";
+	phys = <&comphy0 1>;
+
+	/* enabled by U-Boot if switch or SFP module is present */
+	status = "disabled";
+};
+
+&sdhci0 {
+	wp-inverted;
+	bus-width = <4>;
+	cd-gpios = <&gpionb 10 GPIO_ACTIVE_HIGH>;
+	vqmmc-supply = <&vsdc_reg>;
+	marvell,pad-type = "sd";
+	status = "okay";
+};
+
+&sdhci1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdio_pins>;
+	non-removable;
+	bus-width = <4>;
+	marvell,pad-type = "sd";
+	vqmmc-supply = <&vsdio_reg>;
+	mmc-pwrseq = <&sdhci1_pwrseq>;
+	status = "okay";
+};
+
+&spi0 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi_quad_pins &spi_cs1_pins>;
+	assigned-clocks = <&nb_periph_clk 7>;
+	assigned-clock-parents = <&tbg 1>;
+	assigned-clock-rates = <20000000>;
+
+	spi-flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <20000000>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "secure-firmware";
+				reg = <0x0 0x20000>;
+			};
+
+			partition@20000 {
+				label = "u-boot";
+				reg = <0x20000 0x160000>;
+			};
+
+			partition@180000 {
+				label = "u-boot-env";
+				reg = <0x180000 0x10000>;
+			};
+
+			partition@190000 {
+				label = "Rescue system";
+				reg = <0x190000 0x660000>;
+			};
+
+			partition@7f0000 {
+				label = "dtb";
+				reg = <0x7f0000 0x10000>;
+			};
+		};
+	};
+
+	moxtet: moxtet@1 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "cznic,moxtet";
+		reg = <1>;
+		reset-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>;
+		spi-max-frequency = <10000000>;
+		spi-cpol;
+		spi-cpha;
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		interrupt-parent = <&gpiosb>;
+		interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
+		status = "okay";
+
+		moxtet_sfp: gpio@0 {
+			compatible = "cznic,moxtet-gpio";
+			gpio-controller;
+			#gpio-cells = <2>;
+			reg = <0>;
+			status = "disabled";
+		};
+	};
+};
+
+&usb2 {
+	status = "okay";
+};
+
+&usb3 {
+	status = "okay";
+	phys = <&comphy2 0>;
+	usb-phy = <&usb3_phy>;
+};
+
+&mdio {
+	pinctrl-names = "default";
+	pinctrl-0 = <&smi_pins>;
+	status = "okay";
+
+	phy1: ethernet-phy@1 {
+		reg = <1>;
+	};
+
+	/* switch nodes are enabled by U-Boot if modules are present */
+	switch0@10 {
+		compatible = "marvell,mv88e6190";
+		reg = <0x10 0>;
+		dsa,member = <0 0>;
+		interrupt-parent = <&moxtet>;
+		interrupts = <MOXTET_IRQ_PERIDOT(0)>;
+		status = "disabled";
+
+		mdio {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			switch0phy1: switch0phy1@1 {
+				reg = <0x1>;
+			};
+
+			switch0phy2: switch0phy2@2 {
+				reg = <0x2>;
+			};
+
+			switch0phy3: switch0phy3@3 {
+				reg = <0x3>;
+			};
+
+			switch0phy4: switch0phy4@4 {
+				reg = <0x4>;
+			};
+
+			switch0phy5: switch0phy5@5 {
+				reg = <0x5>;
+			};
+
+			switch0phy6: switch0phy6@6 {
+				reg = <0x6>;
+			};
+
+			switch0phy7: switch0phy7@7 {
+				reg = <0x7>;
+			};
+
+			switch0phy8: switch0phy8@8 {
+				reg = <0x8>;
+			};
+		};
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@1 {
+				reg = <0x1>;
+				label = "lan1";
+				phy-handle = <&switch0phy1>;
+			};
+
+			port@2 {
+				reg = <0x2>;
+				label = "lan2";
+				phy-handle = <&switch0phy2>;
+			};
+
+			port@3 {
+				reg = <0x3>;
+				label = "lan3";
+				phy-handle = <&switch0phy3>;
+			};
+
+			port@4 {
+				reg = <0x4>;
+				label = "lan4";
+				phy-handle = <&switch0phy4>;
+			};
+
+			port@5 {
+				reg = <0x5>;
+				label = "lan5";
+				phy-handle = <&switch0phy5>;
+			};
+
+			port@6 {
+				reg = <0x6>;
+				label = "lan6";
+				phy-handle = <&switch0phy6>;
+			};
+
+			port@7 {
+				reg = <0x7>;
+				label = "lan7";
+				phy-handle = <&switch0phy7>;
+			};
+
+			port@8 {
+				reg = <0x8>;
+				label = "lan8";
+				phy-handle = <&switch0phy8>;
+			};
+
+			port@9 {
+				reg = <0x9>;
+				label = "cpu";
+				ethernet = <&eth1>;
+				phy-mode = "2500base-x";
+				managed = "in-band-status";
+			};
+
+			switch0port10: port@a {
+				reg = <0xa>;
+				label = "dsa";
+				phy-mode = "2500base-x";
+				managed = "in-band-status";
+				link = <&switch1port9 &switch2port9>;
+				status = "disabled";
+			};
+
+			port-sfp@a {
+				reg = <0xa>;
+				label = "sfp";
+				sfp = <&sfp>;
+				phy-mode = "sgmii";
+				managed = "in-band-status";
+				status = "disabled";
+			};
+		};
+	};
+
+	switch0@2 {
+		compatible = "marvell,mv88e6085";
+		reg = <0x2 0>;
+		dsa,member = <0 0>;
+		interrupt-parent = <&moxtet>;
+		interrupts = <MOXTET_IRQ_TOPAZ>;
+		status = "disabled";
+
+		mdio {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			switch0phy1_topaz: switch0phy1@11 {
+				reg = <0x11>;
+			};
+
+			switch0phy2_topaz: switch0phy2@12 {
+				reg = <0x12>;
+			};
+
+			switch0phy3_topaz: switch0phy3@13 {
+				reg = <0x13>;
+			};
+
+			switch0phy4_topaz: switch0phy4@14 {
+				reg = <0x14>;
+			};
+		};
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@1 {
+				reg = <0x1>;
+				label = "lan1";
+				phy-handle = <&switch0phy1_topaz>;
+			};
+
+			port@2 {
+				reg = <0x2>;
+				label = "lan2";
+				phy-handle = <&switch0phy2_topaz>;
+			};
+
+			port@3 {
+				reg = <0x3>;
+				label = "lan3";
+				phy-handle = <&switch0phy3_topaz>;
+			};
+
+			port@4 {
+				reg = <0x4>;
+				label = "lan4";
+				phy-handle = <&switch0phy4_topaz>;
+			};
+
+			port@5 {
+				reg = <0x5>;
+				label = "cpu";
+				phy-mode = "2500base-x";
+				managed = "in-band-status";
+				ethernet = <&eth1>;
+			};
+		};
+	};
+
+	switch1@11 {
+		compatible = "marvell,mv88e6190";
+		reg = <0x11 0>;
+		dsa,member = <0 1>;
+		interrupt-parent = <&moxtet>;
+		interrupts = <MOXTET_IRQ_PERIDOT(1)>;
+		status = "disabled";
+
+		mdio {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			switch1phy1: switch1phy1@1 {
+				reg = <0x1>;
+			};
+
+			switch1phy2: switch1phy2@2 {
+				reg = <0x2>;
+			};
+
+			switch1phy3: switch1phy3@3 {
+				reg = <0x3>;
+			};
+
+			switch1phy4: switch1phy4@4 {
+				reg = <0x4>;
+			};
+
+			switch1phy5: switch1phy5@5 {
+				reg = <0x5>;
+			};
+
+			switch1phy6: switch1phy6@6 {
+				reg = <0x6>;
+			};
+
+			switch1phy7: switch1phy7@7 {
+				reg = <0x7>;
+			};
+
+			switch1phy8: switch1phy8@8 {
+				reg = <0x8>;
+			};
+		};
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@1 {
+				reg = <0x1>;
+				label = "lan9";
+				phy-handle = <&switch1phy1>;
+			};
+
+			port@2 {
+				reg = <0x2>;
+				label = "lan10";
+				phy-handle = <&switch1phy2>;
+			};
+
+			port@3 {
+				reg = <0x3>;
+				label = "lan11";
+				phy-handle = <&switch1phy3>;
+			};
+
+			port@4 {
+				reg = <0x4>;
+				label = "lan12";
+				phy-handle = <&switch1phy4>;
+			};
+
+			port@5 {
+				reg = <0x5>;
+				label = "lan13";
+				phy-handle = <&switch1phy5>;
+			};
+
+			port@6 {
+				reg = <0x6>;
+				label = "lan14";
+				phy-handle = <&switch1phy6>;
+			};
+
+			port@7 {
+				reg = <0x7>;
+				label = "lan15";
+				phy-handle = <&switch1phy7>;
+			};
+
+			port@8 {
+				reg = <0x8>;
+				label = "lan16";
+				phy-handle = <&switch1phy8>;
+			};
+
+			switch1port9: port@9 {
+				reg = <0x9>;
+				label = "dsa";
+				phy-mode = "2500base-x";
+				managed = "in-band-status";
+				link = <&switch0port10>;
+			};
+
+			switch1port10: port@a {
+				reg = <0xa>;
+				label = "dsa";
+				phy-mode = "2500base-x";
+				managed = "in-band-status";
+				link = <&switch2port9>;
+				status = "disabled";
+			};
+
+			port-sfp@a {
+				reg = <0xa>;
+				label = "sfp";
+				sfp = <&sfp>;
+				phy-mode = "sgmii";
+				managed = "in-band-status";
+				status = "disabled";
+			};
+		};
+	};
+
+	switch1@2 {
+		compatible = "marvell,mv88e6085";
+		reg = <0x2 0>;
+		dsa,member = <0 1>;
+		interrupt-parent = <&moxtet>;
+		interrupts = <MOXTET_IRQ_TOPAZ>;
+		status = "disabled";
+
+		mdio {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			switch1phy1_topaz: switch1phy1@11 {
+				reg = <0x11>;
+			};
+
+			switch1phy2_topaz: switch1phy2@12 {
+				reg = <0x12>;
+			};
+
+			switch1phy3_topaz: switch1phy3@13 {
+				reg = <0x13>;
+			};
+
+			switch1phy4_topaz: switch1phy4@14 {
+				reg = <0x14>;
+			};
+		};
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@1 {
+				reg = <0x1>;
+				label = "lan9";
+				phy-handle = <&switch1phy1_topaz>;
+			};
+
+			port@2 {
+				reg = <0x2>;
+				label = "lan10";
+				phy-handle = <&switch1phy2_topaz>;
+			};
+
+			port@3 {
+				reg = <0x3>;
+				label = "lan11";
+				phy-handle = <&switch1phy3_topaz>;
+			};
+
+			port@4 {
+				reg = <0x4>;
+				label = "lan12";
+				phy-handle = <&switch1phy4_topaz>;
+			};
+
+			port@5 {
+				reg = <0x5>;
+				label = "dsa";
+				phy-mode = "2500base-x";
+				managed = "in-band-status";
+				link = <&switch0port10>;
+			};
+		};
+	};
+
+	switch2@12 {
+		compatible = "marvell,mv88e6190";
+		reg = <0x12 0>;
+		dsa,member = <0 2>;
+		interrupt-parent = <&moxtet>;
+		interrupts = <MOXTET_IRQ_PERIDOT(2)>;
+		status = "disabled";
+
+		mdio {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			switch2phy1: switch2phy1@1 {
+				reg = <0x1>;
+			};
+
+			switch2phy2: switch2phy2@2 {
+				reg = <0x2>;
+			};
+
+			switch2phy3: switch2phy3@3 {
+				reg = <0x3>;
+			};
+
+			switch2phy4: switch2phy4@4 {
+				reg = <0x4>;
+			};
+
+			switch2phy5: switch2phy5@5 {
+				reg = <0x5>;
+			};
+
+			switch2phy6: switch2phy6@6 {
+				reg = <0x6>;
+			};
+
+			switch2phy7: switch2phy7@7 {
+				reg = <0x7>;
+			};
+
+			switch2phy8: switch2phy8@8 {
+				reg = <0x8>;
+			};
+		};
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@1 {
+				reg = <0x1>;
+				label = "lan17";
+				phy-handle = <&switch2phy1>;
+			};
+
+			port@2 {
+				reg = <0x2>;
+				label = "lan18";
+				phy-handle = <&switch2phy2>;
+			};
+
+			port@3 {
+				reg = <0x3>;
+				label = "lan19";
+				phy-handle = <&switch2phy3>;
+			};
+
+			port@4 {
+				reg = <0x4>;
+				label = "lan20";
+				phy-handle = <&switch2phy4>;
+			};
+
+			port@5 {
+				reg = <0x5>;
+				label = "lan21";
+				phy-handle = <&switch2phy5>;
+			};
+
+			port@6 {
+				reg = <0x6>;
+				label = "lan22";
+				phy-handle = <&switch2phy6>;
+			};
+
+			port@7 {
+				reg = <0x7>;
+				label = "lan23";
+				phy-handle = <&switch2phy7>;
+			};
+
+			port@8 {
+				reg = <0x8>;
+				label = "lan24";
+				phy-handle = <&switch2phy8>;
+			};
+
+			switch2port9: port@9 {
+				reg = <0x9>;
+				label = "dsa";
+				phy-mode = "2500base-x";
+				managed = "in-band-status";
+				link = <&switch1port10 &switch0port10>;
+			};
+
+			port-sfp@a {
+				reg = <0xa>;
+				label = "sfp";
+				sfp = <&sfp>;
+				phy-mode = "sgmii";
+				managed = "in-band-status";
+				status = "disabled";
+			};
+		};
+	};
+
+	switch2@2 {
+		compatible = "marvell,mv88e6085";
+		reg = <0x2 0>;
+		dsa,member = <0 2>;
+		interrupt-parent = <&moxtet>;
+		interrupts = <MOXTET_IRQ_TOPAZ>;
+		status = "disabled";
+
+		mdio {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			switch2phy1_topaz: switch2phy1@11 {
+				reg = <0x11>;
+			};
+
+			switch2phy2_topaz: switch2phy2@12 {
+				reg = <0x12>;
+			};
+
+			switch2phy3_topaz: switch2phy3@13 {
+				reg = <0x13>;
+			};
+
+			switch2phy4_topaz: switch2phy4@14 {
+				reg = <0x14>;
+			};
+		};
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@1 {
+				reg = <0x1>;
+				label = "lan17";
+				phy-handle = <&switch2phy1_topaz>;
+			};
+
+			port@2 {
+				reg = <0x2>;
+				label = "lan18";
+				phy-handle = <&switch2phy2_topaz>;
+			};
+
+			port@3 {
+				reg = <0x3>;
+				label = "lan19";
+				phy-handle = <&switch2phy3_topaz>;
+			};
+
+			port@4 {
+				reg = <0x4>;
+				label = "lan20";
+				phy-handle = <&switch2phy4_topaz>;
+			};
+
+			port@5 {
+				reg = <0x5>;
+				label = "dsa";
+				phy-mode = "2500base-x";
+				managed = "in-band-status";
+				link = <&switch1port10 &switch0port10>;
+			};
+		};
+	};
+};
-- 
2.21.0

Re: [PATCH mvebu-dt64 3/3] arm64: dts: marvell: add DTS for Turris Mox

[Gregory CLEMENT]

Hi Marek,

> This adds support for the Turris Mox board from CZ.NIC.
>
> Turris Mox is as modular router based on the Armada 3720 SOC (same as
> EspressoBin).
>
> The basic board can be extended by different modules.
> If those are connected, U-Boot lets the kernel know via device-tree.
>
> Since modules can be connected in different order and some modules can
> be connected multiple times (up to three modules containing 8-port
> ethernet switch in DSA configuration can be connected) we decided
> against using device-tree overlays, because it got complicated rather
> quickly. (For example the SFP module can be connected directly to the
> CPU, or after a switch module. There are four cases and all would need
> different SFP overlay. There are two types of switch modules (8-port
> with pass-through and 4-port with no pass-through). For those we would
> again need at least 6 more overlays.)
>
> We therefore decided to put all the possibly connected devices in one
> device-tree and disable them by default. When U-Boot finds out which
> modules are connected, it fixes the loaded device-tree accordingly just
> before boot. By Rob Herring's suggestion we also made it so that U-Boot
> completely removes nodes which are disabled after this fixup.
>

This device tree looks sane for me I didn't see any issue, however I
would like to have the review from Andrew who know better all the switch
part.

Thanks,

Gregory

> Signed-off-by: Marek Behún <marek.behun@nic.cz>
> Cc: Rob Herring <robh@kernel.org>
> Cc: devicetree@vger.kernel.org
> Cc: Gregory CLEMENT <gregory.clement@bootlin.com>
> ---
>  arch/arm64/boot/dts/marvell/Makefile          |   1 +
>  .../dts/marvell/armada-3720-turris-mox.dts    | 841 ++++++++++++++++++
>  2 files changed, 842 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts
>
> diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile
> index caed4334f27d..243338c914a4 100644
> --- a/arch/arm64/boot/dts/marvell/Makefile
> +++ b/arch/arm64/boot/dts/marvell/Makefile
> @@ -2,6 +2,7 @@
>  # Mvebu SoC Family
>  dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-db.dtb
>  dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-espressobin.dtb
> +dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-turris-mox.dtb
>  dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-uDPU.dtb
>  dtb-$(CONFIG_ARCH_MVEBU) += armada-7040-db.dtb
>  dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-clearfog-gt-8k.dtb
> diff --git a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts
> new file mode 100644
> index 000000000000..32ed2bbdab27
> --- /dev/null
> +++ b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts
> @@ -0,0 +1,841 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Device Tree file for CZ.NIC Turris Mox Board
> + * 2019 by Marek Behun <marek.behun@nic.cz>
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/bus/moxtet.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +#include "armada-372x.dtsi"
> +
> +/ {
> +	model = "CZ.NIC Turris Mox Board";
> +	compatible = "cznic,turris-mox", "marvell,armada3720",
> +		     "marvell,armada3710";
> +
> +	aliases {
> +		spi0 = &spi0;
> +		ethernet1 = &eth1;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +
> +	memory@0 {
> +		device_type = "memory";
> +		reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
> +	};
> +
> +	leds {
> +		compatible = "gpio-leds";
> +		red {
> +			gpios = <&gpiosb 21 GPIO_ACTIVE_LOW>;
> +			linux,default-trigger = "default-on";
> +		};
> +	};
> +
> +	gpio-keys {
> +		compatible = "gpio-keys";
> +
> +		reset {
> +			label = "reset";
> +			linux,code = <BTN_MISC>;
> +			gpios = <&gpiosb 20 GPIO_ACTIVE_LOW>;
> +			debounce-interval = <60>;
> +		};
> +	};
> +
> +	exp_usb3_vbus: usb3-vbus {
> +		compatible = "regulator-fixed";
> +		regulator-name = "usb3-vbus";
> +		regulator-min-microvolt = <5000000>;
> +		regulator-max-microvolt = <5000000>;
> +		enable-active-high;
> +		regulator-always-on;
> +		gpio = <&gpiosb 0 GPIO_ACTIVE_HIGH>;
> +	};
> +
> +	usb3_phy: usb3-phy {
> +		compatible = "usb-nop-xceiv";
> +		vcc-supply = <&exp_usb3_vbus>;
> +	};
> +
> +	vsdc_reg: vsdc-reg {
> +		compatible = "regulator-gpio";
> +		regulator-name = "vsdc";
> +		regulator-min-microvolt = <1800000>;
> +		regulator-max-microvolt = <3300000>;
> +		regulator-boot-on;
> +
> +		gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>;
> +		gpios-states = <0>;
> +		states = <1800000 0x1
> +			  3300000 0x0>;
> +		enable-active-high;
> +	};
> +
> +	vsdio_reg: vsdio-reg {
> +		compatible = "regulator-gpio";
> +		regulator-name = "vsdio";
> +		regulator-min-microvolt = <1800000>;
> +		regulator-max-microvolt = <3300000>;
> +		regulator-boot-on;
> +
> +		gpios = <&gpiosb 22 GPIO_ACTIVE_HIGH>;
> +		gpios-states = <0>;
> +		states = <1800000 0x1
> +			  3300000 0x0>;
> +		enable-active-high;
> +	};
> +
> +	sdhci1_pwrseq: sdhci1-pwrseq {
> +		compatible = "mmc-pwrseq-simple";
> +		reset-gpios = <&gpionb 19 GPIO_ACTIVE_HIGH>;
> +		status = "okay";
> +	};
> +
> +	sfp: sfp {
> +		compatible = "sff,sfp+";
> +		i2c-bus = <&i2c0>;
> +		los-gpio = <&moxtet_sfp 0 GPIO_ACTIVE_HIGH>;
> +		tx-fault-gpio = <&moxtet_sfp 1 GPIO_ACTIVE_HIGH>;
> +		mod-def0-gpio = <&moxtet_sfp 2 GPIO_ACTIVE_LOW>;
> +		tx-disable-gpio = <&moxtet_sfp 4 GPIO_ACTIVE_HIGH>;
> +		rate-select0-gpio = <&moxtet_sfp 5 GPIO_ACTIVE_HIGH>;
> +
> +		/* enabled by U-Boot if SFP module is present */
> +		status = "disabled";
> +	};
> +};
> +
> +&i2c0 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&i2c1_pins>;
> +	status = "okay";
> +
> +	rtc@6f {
> +		compatible = "microchip,mcp7940x";
> +		reg = <0x6f>;
> +	};
> +};
> +
> +&pcie_reset_pins {
> +	function = "gpio";
> +};
> +
> +&pcie0 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
> +	status = "okay";
> +	max-link-speed = <2>;
> +	reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
> +	phys = <&comphy1 0>;
> +
> +	/* enabled by U-Boot if PCIe module is present */
> +	status = "disabled";
> +};
> +
> +&uart0 {
> +	status = "okay";
> +};
> +
> +&eth0 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&rgmii_pins>;
> +	phy-mode = "rgmii-id";
> +	phy = <&phy1>;
> +	status = "okay";
> +};
> +
> +&eth1 {
> +	phy-mode = "2500base-x";
> +	managed = "in-band-status";
> +	phys = <&comphy0 1>;
> +
> +	/* enabled by U-Boot if switch or SFP module is present */
> +	status = "disabled";
> +};
> +
> +&sdhci0 {
> +	wp-inverted;
> +	bus-width = <4>;
> +	cd-gpios = <&gpionb 10 GPIO_ACTIVE_HIGH>;
> +	vqmmc-supply = <&vsdc_reg>;
> +	marvell,pad-type = "sd";
> +	status = "okay";
> +};
> +
> +&sdhci1 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&sdio_pins>;
> +	non-removable;
> +	bus-width = <4>;
> +	marvell,pad-type = "sd";
> +	vqmmc-supply = <&vsdio_reg>;
> +	mmc-pwrseq = <&sdhci1_pwrseq>;
> +	status = "okay";
> +};
> +
> +&spi0 {
> +	status = "okay";
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&spi_quad_pins &spi_cs1_pins>;
> +	assigned-clocks = <&nb_periph_clk 7>;
> +	assigned-clock-parents = <&tbg 1>;
> +	assigned-clock-rates = <20000000>;
> +
> +	spi-flash@0 {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		compatible = "jedec,spi-nor";
> +		reg = <0>;
> +		spi-max-frequency = <20000000>;
> +
> +		partitions {
> +			compatible = "fixed-partitions";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +
> +			partition@0 {
> +				label = "secure-firmware";
> +				reg = <0x0 0x20000>;
> +			};
> +
> +			partition@20000 {
> +				label = "u-boot";
> +				reg = <0x20000 0x160000>;
> +			};
> +
> +			partition@180000 {
> +				label = "u-boot-env";
> +				reg = <0x180000 0x10000>;
> +			};
> +
> +			partition@190000 {
> +				label = "Rescue system";
> +				reg = <0x190000 0x660000>;
> +			};
> +
> +			partition@7f0000 {
> +				label = "dtb";
> +				reg = <0x7f0000 0x10000>;
> +			};
> +		};
> +	};
> +
> +	moxtet: moxtet@1 {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		compatible = "cznic,moxtet";
> +		reg = <1>;
> +		reset-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>;
> +		spi-max-frequency = <10000000>;
> +		spi-cpol;
> +		spi-cpha;
> +		interrupt-controller;
> +		#interrupt-cells = <1>;
> +		interrupt-parent = <&gpiosb>;
> +		interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
> +		status = "okay";
> +
> +		moxtet_sfp: gpio@0 {
> +			compatible = "cznic,moxtet-gpio";
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			reg = <0>;
> +			status = "disabled";
> +		};
> +	};
> +};
> +
> +&usb2 {
> +	status = "okay";
> +};
> +
> +&usb3 {
> +	status = "okay";
> +	phys = <&comphy2 0>;
> +	usb-phy = <&usb3_phy>;
> +};
> +
> +&mdio {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&smi_pins>;
> +	status = "okay";
> +
> +	phy1: ethernet-phy@1 {
> +		reg = <1>;
> +	};
> +
> +	/* switch nodes are enabled by U-Boot if modules are present */
> +	switch0@10 {
> +		compatible = "marvell,mv88e6190";
> +		reg = <0x10 0>;
> +		dsa,member = <0 0>;
> +		interrupt-parent = <&moxtet>;
> +		interrupts = <MOXTET_IRQ_PERIDOT(0)>;
> +		status = "disabled";
> +
> +		mdio {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			switch0phy1: switch0phy1@1 {
> +				reg = <0x1>;
> +			};
> +
> +			switch0phy2: switch0phy2@2 {
> +				reg = <0x2>;
> +			};
> +
> +			switch0phy3: switch0phy3@3 {
> +				reg = <0x3>;
> +			};
> +
> +			switch0phy4: switch0phy4@4 {
> +				reg = <0x4>;
> +			};
> +
> +			switch0phy5: switch0phy5@5 {
> +				reg = <0x5>;
> +			};
> +
> +			switch0phy6: switch0phy6@6 {
> +				reg = <0x6>;
> +			};
> +
> +			switch0phy7: switch0phy7@7 {
> +				reg = <0x7>;
> +			};
> +
> +			switch0phy8: switch0phy8@8 {
> +				reg = <0x8>;
> +			};
> +		};
> +
> +		ports {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			port@1 {
> +				reg = <0x1>;
> +				label = "lan1";
> +				phy-handle = <&switch0phy1>;
> +			};
> +
> +			port@2 {
> +				reg = <0x2>;
> +				label = "lan2";
> +				phy-handle = <&switch0phy2>;
> +			};
> +
> +			port@3 {
> +				reg = <0x3>;
> +				label = "lan3";
> +				phy-handle = <&switch0phy3>;
> +			};
> +
> +			port@4 {
> +				reg = <0x4>;
> +				label = "lan4";
> +				phy-handle = <&switch0phy4>;
> +			};
> +
> +			port@5 {
> +				reg = <0x5>;
> +				label = "lan5";
> +				phy-handle = <&switch0phy5>;
> +			};
> +
> +			port@6 {
> +				reg = <0x6>;
> +				label = "lan6";
> +				phy-handle = <&switch0phy6>;
> +			};
> +
> +			port@7 {
> +				reg = <0x7>;
> +				label = "lan7";
> +				phy-handle = <&switch0phy7>;
> +			};
> +
> +			port@8 {
> +				reg = <0x8>;
> +				label = "lan8";
> +				phy-handle = <&switch0phy8>;
> +			};
> +
> +			port@9 {
> +				reg = <0x9>;
> +				label = "cpu";
> +				ethernet = <&eth1>;
> +				phy-mode = "2500base-x";
> +				managed = "in-band-status";
> +			};
> +
> +			switch0port10: port@a {
> +				reg = <0xa>;
> +				label = "dsa";
> +				phy-mode = "2500base-x";
> +				managed = "in-band-status";
> +				link = <&switch1port9 &switch2port9>;
> +				status = "disabled";
> +			};
> +
> +			port-sfp@a {
> +				reg = <0xa>;
> +				label = "sfp";
> +				sfp = <&sfp>;
> +				phy-mode = "sgmii";
> +				managed = "in-band-status";
> +				status = "disabled";
> +			};
> +		};
> +	};
> +
> +	switch0@2 {
> +		compatible = "marvell,mv88e6085";
> +		reg = <0x2 0>;
> +		dsa,member = <0 0>;
> +		interrupt-parent = <&moxtet>;
> +		interrupts = <MOXTET_IRQ_TOPAZ>;
> +		status = "disabled";
> +
> +		mdio {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			switch0phy1_topaz: switch0phy1@11 {
> +				reg = <0x11>;
> +			};
> +
> +			switch0phy2_topaz: switch0phy2@12 {
> +				reg = <0x12>;
> +			};
> +
> +			switch0phy3_topaz: switch0phy3@13 {
> +				reg = <0x13>;
> +			};
> +
> +			switch0phy4_topaz: switch0phy4@14 {
> +				reg = <0x14>;
> +			};
> +		};
> +
> +		ports {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			port@1 {
> +				reg = <0x1>;
> +				label = "lan1";
> +				phy-handle = <&switch0phy1_topaz>;
> +			};
> +
> +			port@2 {
> +				reg = <0x2>;
> +				label = "lan2";
> +				phy-handle = <&switch0phy2_topaz>;
> +			};
> +
> +			port@3 {
> +				reg = <0x3>;
> +				label = "lan3";
> +				phy-handle = <&switch0phy3_topaz>;
> +			};
> +
> +			port@4 {
> +				reg = <0x4>;
> +				label = "lan4";
> +				phy-handle = <&switch0phy4_topaz>;
> +			};
> +
> +			port@5 {
> +				reg = <0x5>;
> +				label = "cpu";
> +				phy-mode = "2500base-x";
> +				managed = "in-band-status";
> +				ethernet = <&eth1>;
> +			};
> +		};
> +	};
> +
> +	switch1@11 {
> +		compatible = "marvell,mv88e6190";
> +		reg = <0x11 0>;
> +		dsa,member = <0 1>;
> +		interrupt-parent = <&moxtet>;
> +		interrupts = <MOXTET_IRQ_PERIDOT(1)>;
> +		status = "disabled";
> +
> +		mdio {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			switch1phy1: switch1phy1@1 {
> +				reg = <0x1>;
> +			};
> +
> +			switch1phy2: switch1phy2@2 {
> +				reg = <0x2>;
> +			};
> +
> +			switch1phy3: switch1phy3@3 {
> +				reg = <0x3>;
> +			};
> +
> +			switch1phy4: switch1phy4@4 {
> +				reg = <0x4>;
> +			};
> +
> +			switch1phy5: switch1phy5@5 {
> +				reg = <0x5>;
> +			};
> +
> +			switch1phy6: switch1phy6@6 {
> +				reg = <0x6>;
> +			};
> +
> +			switch1phy7: switch1phy7@7 {
> +				reg = <0x7>;
> +			};
> +
> +			switch1phy8: switch1phy8@8 {
> +				reg = <0x8>;
> +			};
> +		};
> +
> +		ports {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			port@1 {
> +				reg = <0x1>;
> +				label = "lan9";
> +				phy-handle = <&switch1phy1>;
> +			};
> +
> +			port@2 {
> +				reg = <0x2>;
> +				label = "lan10";
> +				phy-handle = <&switch1phy2>;
> +			};
> +
> +			port@3 {
> +				reg = <0x3>;
> +				label = "lan11";
> +				phy-handle = <&switch1phy3>;
> +			};
> +
> +			port@4 {
> +				reg = <0x4>;
> +				label = "lan12";
> +				phy-handle = <&switch1phy4>;
> +			};
> +
> +			port@5 {
> +				reg = <0x5>;
> +				label = "lan13";
> +				phy-handle = <&switch1phy5>;
> +			};
> +
> +			port@6 {
> +				reg = <0x6>;
> +				label = "lan14";
> +				phy-handle = <&switch1phy6>;
> +			};
> +
> +			port@7 {
> +				reg = <0x7>;
> +				label = "lan15";
> +				phy-handle = <&switch1phy7>;
> +			};
> +
> +			port@8 {
> +				reg = <0x8>;
> +				label = "lan16";
> +				phy-handle = <&switch1phy8>;
> +			};
> +
> +			switch1port9: port@9 {
> +				reg = <0x9>;
> +				label = "dsa";
> +				phy-mode = "2500base-x";
> +				managed = "in-band-status";
> +				link = <&switch0port10>;
> +			};
> +
> +			switch1port10: port@a {
> +				reg = <0xa>;
> +				label = "dsa";
> +				phy-mode = "2500base-x";
> +				managed = "in-band-status";
> +				link = <&switch2port9>;
> +				status = "disabled";
> +			};
> +
> +			port-sfp@a {
> +				reg = <0xa>;
> +				label = "sfp";
> +				sfp = <&sfp>;
> +				phy-mode = "sgmii";
> +				managed = "in-band-status";
> +				status = "disabled";
> +			};
> +		};
> +	};
> +
> +	switch1@2 {
> +		compatible = "marvell,mv88e6085";
> +		reg = <0x2 0>;
> +		dsa,member = <0 1>;
> +		interrupt-parent = <&moxtet>;
> +		interrupts = <MOXTET_IRQ_TOPAZ>;
> +		status = "disabled";
> +
> +		mdio {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			switch1phy1_topaz: switch1phy1@11 {
> +				reg = <0x11>;
> +			};
> +
> +			switch1phy2_topaz: switch1phy2@12 {
> +				reg = <0x12>;
> +			};
> +
> +			switch1phy3_topaz: switch1phy3@13 {
> +				reg = <0x13>;
> +			};
> +
> +			switch1phy4_topaz: switch1phy4@14 {
> +				reg = <0x14>;
> +			};
> +		};
> +
> +		ports {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			port@1 {
> +				reg = <0x1>;
> +				label = "lan9";
> +				phy-handle = <&switch1phy1_topaz>;
> +			};
> +
> +			port@2 {
> +				reg = <0x2>;
> +				label = "lan10";
> +				phy-handle = <&switch1phy2_topaz>;
> +			};
> +
> +			port@3 {
> +				reg = <0x3>;
> +				label = "lan11";
> +				phy-handle = <&switch1phy3_topaz>;
> +			};
> +
> +			port@4 {
> +				reg = <0x4>;
> +				label = "lan12";
> +				phy-handle = <&switch1phy4_topaz>;
> +			};
> +
> +			port@5 {
> +				reg = <0x5>;
> +				label = "dsa";
> +				phy-mode = "2500base-x";
> +				managed = "in-band-status";
> +				link = <&switch0port10>;
> +			};
> +		};
> +	};
> +
> +	switch2@12 {
> +		compatible = "marvell,mv88e6190";
> +		reg = <0x12 0>;
> +		dsa,member = <0 2>;
> +		interrupt-parent = <&moxtet>;
> +		interrupts = <MOXTET_IRQ_PERIDOT(2)>;
> +		status = "disabled";
> +
> +		mdio {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			switch2phy1: switch2phy1@1 {
> +				reg = <0x1>;
> +			};
> +
> +			switch2phy2: switch2phy2@2 {
> +				reg = <0x2>;
> +			};
> +
> +			switch2phy3: switch2phy3@3 {
> +				reg = <0x3>;
> +			};
> +
> +			switch2phy4: switch2phy4@4 {
> +				reg = <0x4>;
> +			};
> +
> +			switch2phy5: switch2phy5@5 {
> +				reg = <0x5>;
> +			};
> +
> +			switch2phy6: switch2phy6@6 {
> +				reg = <0x6>;
> +			};
> +
> +			switch2phy7: switch2phy7@7 {
> +				reg = <0x7>;
> +			};
> +
> +			switch2phy8: switch2phy8@8 {
> +				reg = <0x8>;
> +			};
> +		};
> +
> +		ports {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			port@1 {
> +				reg = <0x1>;
> +				label = "lan17";
> +				phy-handle = <&switch2phy1>;
> +			};
> +
> +			port@2 {
> +				reg = <0x2>;
> +				label = "lan18";
> +				phy-handle = <&switch2phy2>;
> +			};
> +
> +			port@3 {
> +				reg = <0x3>;
> +				label = "lan19";
> +				phy-handle = <&switch2phy3>;
> +			};
> +
> +			port@4 {
> +				reg = <0x4>;
> +				label = "lan20";
> +				phy-handle = <&switch2phy4>;
> +			};
> +
> +			port@5 {
> +				reg = <0x5>;
> +				label = "lan21";
> +				phy-handle = <&switch2phy5>;
> +			};
> +
> +			port@6 {
> +				reg = <0x6>;
> +				label = "lan22";
> +				phy-handle = <&switch2phy6>;
> +			};
> +
> +			port@7 {
> +				reg = <0x7>;
> +				label = "lan23";
> +				phy-handle = <&switch2phy7>;
> +			};
> +
> +			port@8 {
> +				reg = <0x8>;
> +				label = "lan24";
> +				phy-handle = <&switch2phy8>;
> +			};
> +
> +			switch2port9: port@9 {
> +				reg = <0x9>;
> +				label = "dsa";
> +				phy-mode = "2500base-x";
> +				managed = "in-band-status";
> +				link = <&switch1port10 &switch0port10>;
> +			};
> +
> +			port-sfp@a {
> +				reg = <0xa>;
> +				label = "sfp";
> +				sfp = <&sfp>;
> +				phy-mode = "sgmii";
> +				managed = "in-band-status";
> +				status = "disabled";
> +			};
> +		};
> +	};
> +
> +	switch2@2 {
> +		compatible = "marvell,mv88e6085";
> +		reg = <0x2 0>;
> +		dsa,member = <0 2>;
> +		interrupt-parent = <&moxtet>;
> +		interrupts = <MOXTET_IRQ_TOPAZ>;
> +		status = "disabled";
> +
> +		mdio {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			switch2phy1_topaz: switch2phy1@11 {
> +				reg = <0x11>;
> +			};
> +
> +			switch2phy2_topaz: switch2phy2@12 {
> +				reg = <0x12>;
> +			};
> +
> +			switch2phy3_topaz: switch2phy3@13 {
> +				reg = <0x13>;
> +			};
> +
> +			switch2phy4_topaz: switch2phy4@14 {
> +				reg = <0x14>;
> +			};
> +		};
> +
> +		ports {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			port@1 {
> +				reg = <0x1>;
> +				label = "lan17";
> +				phy-handle = <&switch2phy1_topaz>;
> +			};
> +
> +			port@2 {
> +				reg = <0x2>;
> +				label = "lan18";
> +				phy-handle = <&switch2phy2_topaz>;
> +			};
> +
> +			port@3 {
> +				reg = <0x3>;
> +				label = "lan19";
> +				phy-handle = <&switch2phy3_topaz>;
> +			};
> +
> +			port@4 {
> +				reg = <0x4>;
> +				label = "lan20";
> +				phy-handle = <&switch2phy4_topaz>;
> +			};
> +
> +			port@5 {
> +				reg = <0x5>;
> +				label = "dsa";
> +				phy-mode = "2500base-x";
> +				managed = "in-band-status";
> +				link = <&switch1port10 &switch0port10>;
> +			};
> +		};
> +	};
> +};
> -- 
> 2.21.0
>

-- 
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com

Re: [PATCH mvebu-dt64 3/3] arm64: dts: marvell: add DTS for Turris Mox

[Andrew Lunn]

> > +	leds {
> > +		compatible = "gpio-leds";
> > +		red {
> > +			gpios = <&gpiosb 21 GPIO_ACTIVE_LOW>;
> > +			linux,default-trigger = "default-on";
> > +		};

I think there would normally be a label here, so the LED has a
name. There is a convention to follow, which is in the documentation.

> > +	};
> > +
> > +	gpio-keys {
> > +		compatible = "gpio-keys";
> > +
> > +		reset {
> > +			label = "reset";
> > +			linux,code = <BTN_MISC>;

I'm pretty sure there is a linux,code for reset.

> > +			gpios = <&gpiosb 20 GPIO_ACTIVE_LOW>;
> > +			debounce-interval = <60>;
> > +		};
> > +	};

> > +
> > +	sfp: sfp {
> > +		compatible = "sff,sfp+";
> > +		i2c-bus = <&i2c0>;

The standard for SFPs sets the maximum bus speed is 100Khz. I'm sure
some can do 400Khz, but if you want to support all SFPs, you should
use the lower speed. I don't see anywhere in this file where you set
the maximum speed. Maybe the bus defaults to 100K so you don't need
anything?

> > +		los-gpio = <&moxtet_sfp 0 GPIO_ACTIVE_HIGH>;
> > +		tx-fault-gpio = <&moxtet_sfp 1 GPIO_ACTIVE_HIGH>;
> > +		mod-def0-gpio = <&moxtet_sfp 2 GPIO_ACTIVE_LOW>;
> > +		tx-disable-gpio = <&moxtet_sfp 4 GPIO_ACTIVE_HIGH>;
> > +		rate-select0-gpio = <&moxtet_sfp 5 GPIO_ACTIVE_HIGH>;
> > +
> > +		/* enabled by U-Boot if SFP module is present */
> > +		status = "disabled";
> > +	};
> > +};
> > +
> > +&i2c0 {
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&i2c1_pins>;

The node is called i2c0, but here you have i2c1_pins?

> > +	status = "okay";
> > +
> > +	rtc@6f {
> > +		compatible = "microchip,mcp7940x";
> > +		reg = <0x6f>;
> > +	};
> > +};
> > +
> > +&pcie_reset_pins {
> > +	function = "gpio";
> > +};

Should there be something to indicate which GPIO?

> > +&mdio {
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&smi_pins>;
> > +	status = "okay";
> > +
> > +	phy1: ethernet-phy@1 {
> > +		reg = <1>;
> > +	};
> > +
> > +	/* switch nodes are enabled by U-Boot if modules are present */
> > +	switch0@10 {
> > +		compatible = "marvell,mv88e6190";
> > +		reg = <0x10 0>;
> > +		dsa,member = <0 0>;
> > +		interrupt-parent = <&moxtet>;
> > +		interrupts = <MOXTET_IRQ_PERIDOT(0)>;
> > +		status = "disabled";
> > +
> > +		mdio {

> > +		ports {

> > +			switch0port10: port@a {
> > +				reg = <0xa>;
> > +				label = "dsa";
> > +				phy-mode = "2500base-x";
> > +				managed = "in-band-status";
> > +				link = <&switch1port9 &switch2port9>;

Does u-boot also modify this, if switch2 does not exist? I don't know
if it actually matters, but if the switch does not exist, but the
routing entry exists, this switch might still send it frames and use
up some of your bandwidth?

   Andrew

Re: [PATCH mvebu-dt64 3/3] arm64: dts: marvell: add DTS for Turris Mox

[Marek Behún]

On Wed, 28 Aug 2019 14:19:09 +0200
Andrew Lunn <andrew@lunn.ch> wrote:

> > > +	leds {
> > > +		compatible = "gpio-leds";
> > > +		red {
> > > +			gpios = <&gpiosb 21 GPIO_ACTIVE_LOW>;
> > > +			linux,default-trigger = "default-on";
> > > +		};  
> 
> I think there would normally be a label here, so the LED has a
> name. There is a convention to follow, which is in the documentation.

I shall rename it to "mox:red:activity" according to convetion.

> > > +	};
> > > +
> > > +	gpio-keys {
> > > +		compatible = "gpio-keys";
> > > +
> > > +		reset {
> > > +			label = "reset";
> > > +			linux,code = <BTN_MISC>;  
> 
> I'm pretty sure there is a linux,code for reset.

KEY_RESTART

> 
> > > +			gpios = <&gpiosb 20 GPIO_ACTIVE_LOW>;
> > > +			debounce-interval = <60>;
> > > +		};
> > > +	};  
> 
> > > +
> > > +	sfp: sfp {
> > > +		compatible = "sff,sfp+";
> > > +		i2c-bus = <&i2c0>;  
> 
> The standard for SFPs sets the maximum bus speed is 100Khz. I'm sure
> some can do 400Khz, but if you want to support all SFPs, you should
> use the lower speed. I don't see anywhere in this file where you set
> the maximum speed. Maybe the bus defaults to 100K so you don't need
> anything?

Ill add it to i2c0

> > > +
> > > +&i2c0 {
> > > +	pinctrl-names = "default";
> > > +	pinctrl-0 = <&i2c1_pins>;  
> 
> The node is called i2c0, but here you have i2c1_pins?

That is how this is defined in armada-37xx.dtsi. First i2c has
phandle pointer called i2c0, second i2c1. But the pinctrl drivers uses
i2c1 and i2c2. All device trees need to be changed for this. This can
be done later in a separate commit for all device trees using
armada-37xx.dtsi

> > > +	status = "okay";
> > > +
> > > +	rtc@6f {
> > > +		compatible = "microchip,mcp7940x";
> > > +		reg = <0x6f>;
> > > +	};
> > > +};
> > > +
> > > +&pcie_reset_pins {
> > > +	function = "gpio";
> > > +};  
> 
> Should there be something to indicate which GPIO?

No. The thing here is that the function here should remain "pcie"
ideally. When that pin is configured in pcie mode, modifying specific
pcie register should control the pin. But for some reason on our SOC it
does not. I suspect it does not work for Miquel Raynal either, since he
sent patches for aardvark that use reset-gpio as well (see
https://lkml.org/lkml/2018/12/12/242 ).
So we configure it in gpio mode and than in the pcie node we have
  reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;

> > +		ports {  
> 
> > > +			switch0port10: port@a {
> > > +				reg = <0xa>;
> > > +				label = "dsa";
> > > +				phy-mode = "2500base-x";
> > > +				managed = "in-band-status";
> > > +				link = <&switch1port9
> > > &switch2port9>;  
> 
> Does u-boot also modify this, if switch2 does not exist? I don't know
> if it actually matters, but if the switch does not exist, but the
> routing entry exists, this switch might still send it frames and use
> up some of your bandwidth?

That port has status = "disabled" by default. U-Boot enables that node
if second switch is present. U-Boot removes all disabled nodes before
boot. Even if it did not, kernel ignores disabled nodes here.

Marek