From: Roger Lu <roger.lu@mediatek.com>
To: Kevin Hilman <khilman@kernel.org>,
Rob Herring <robh+dt@kernel.org>,
Nicolas Boichat <drinkcat@google.com>,
Stephen Boyd <sboyd@kernel.org>
Cc: Fan Chen <fan.chen@mediatek.com>,
HenryC Chen <HenryC.Chen@mediatek.com>,
yt.lee@mediatek.com, Angus Lin <Angus.Lin@mediatek.com>,
Mark Rutland <mark.rutland@arm.com>,
Matthias Brugger <matthias.bgg@gmail.com>,
Nishanth Menon <nm@ti.com>, Roger Lu <roger.lu@mediatek.com>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-pm@vger.kernel.org
Subject: [PATCH v5 2/3] arm64: dts: mt8183: add svs device information
Date: Fri, 6 Sep 2019 18:05:14 +0800 [thread overview]
Message-ID: <20190906100514.30803-3-roger.lu@mediatek.com> (raw)
In-Reply-To: <20190906100514.30803-1-roger.lu@mediatek.com>
Add pmic/clock/irq/efuse setting in svs noce
Signed-off-by: Roger Lu <roger.lu@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 16 +++++++++
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 38 +++++++++++++++++++++
2 files changed, 54 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
index d8e555cbb5d3..7c1d6e6a2a85 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
@@ -135,6 +135,22 @@
};
+&svs_cpu_little {
+ vcpu-little-supply = <&mt6358_vproc12_reg>;
+};
+
+&svs_cpu_big {
+ vcpu-big-supply = <&mt6358_vproc11_reg>;
+};
+
+&svs_cci {
+ vcci-supply = <&mt6358_vproc12_reg>;
+};
+
+&svs_gpu {
+ vgpu-spply = <&mt6358_vgpu_reg>;
+};
+
&uart0 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 66aaa07f6cec..48343328bec2 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -351,6 +351,39 @@
status = "disabled";
};
+ svs: svs@1100b000 {
+ compatible = "mediatek,mt8183-svs";
+ reg = <0 0x1100b000 0 0x1000>;
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infracfg CLK_INFRA_THERM>;
+ clock-names = "main_clk";
+ nvmem-cells = <&svs_calibration>,
+ <&thermal_calibration>;
+ nvmem-cell-names = "svs-calibration-data",
+ "calibration-data";
+
+ svs_cpu_little: svs_cpu_little {
+ compatible = "mediatek,mt8183-svs-cpu-little";
+ operating-points-v2 = <&cluster0_opp>;
+ };
+
+ svs_cpu_big: svs_cpu_big {
+ compatible = "mediatek,mt8183-svs-cpu-big";
+ operating-points-v2 = <&cluster1_opp>;
+ };
+
+ svs_cci: svs_cci {
+ compatible = "mediatek,mt8183-svs-cci";
+ operating-points-v2 = <&cci_opp>;
+ };
+
+ svs_gpu: svs_gpu {
+ compatible = "mediatek,mt8183-svs-gpu";
+ power-domains = <&scpsys MT8183_POWER_DOMAIN_MFG_2D>;
+ operating-points-v2 = <&gpu_opp_table>;
+ };
+ };
+
spi0: spi@1100a000 {
compatible = "mediatek,mt8183-spi";
#address-cells = <1>;
@@ -439,6 +472,11 @@
compatible = "mediatek,mt8183-efuse",
"mediatek,efuse";
reg = <0 0x11f10000 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ svs_calibration: calib@580 {
+ reg = <0x580 0x64>;
+ };
};
mfgcfg: syscon@13000000 {
--
2.18.0
next prev parent reply other threads:[~2019-09-06 10:05 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-06 10:05 [PATCH v5 0/3] PM / AVS: SVS: Introduce SVS engine Roger Lu
2019-09-06 10:05 ` [PATCH v5 1/3] dt-bindings: soc: add mtk svs dt-bindings Roger Lu
2019-09-30 13:35 ` Rob Herring
2019-12-27 6:50 ` Roger Lu
2020-01-13 7:02 ` Nicolas Boichat
2019-09-06 10:05 ` Roger Lu [this message]
2019-09-06 10:05 ` [PATCH v5 3/3] PM / AVS: SVS: Introduce SVS engine Roger Lu
2019-09-26 22:39 ` Kevin Hilman
2020-01-03 5:44 ` Roger Lu
2019-10-21 7:51 ` Pi-Hsun Shih
2019-11-01 6:10 ` Roger Lu
2019-11-14 7:41 ` Pi-Hsun Shih
2019-12-27 7:14 ` Roger Lu
2019-09-06 10:15 ` [PATCH v5 0/3] " Roger Lu
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