From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jerry-ch Chen Subject: [RFC PATCH V3 2/3] dts: arm64: mt8183: Add FD nodes Date: Fri, 6 Sep 2019 18:11:24 +0800 Message-ID: <20190906101125.3784-3-Jerry-Ch.chen@mediatek.com> References: <20190906101125.3784-1-Jerry-Ch.chen@mediatek.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20190906101125.3784-1-Jerry-Ch.chen@mediatek.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: hans.verkuil@cisco.com, laurent.pinchart+renesas@ideasonboard.com, tfiga@chromium.org, matthias.bgg@gmail.com, mchehab@kernel.org, lkml@metux.net Cc: devicetree@vger.kernel.org, Sean.Cheng@mediatek.com, Rynn.Wu@mediatek.com, srv_heupstream@mediatek.com, po-yang.huang@mediatek.com, Jerry-ch Chen , jungo.lin@mediatek.com, sj.huang@mediatek.com, yuzhao@chromium.org, linux-mediatek@lists.infradead.org, zwisler@chromium.org, ck.hu@mediatek.com, christie.yu@mediatek.com, frederic.chen@mediatek.com, linux-arm-kernel@lists.infradead.org, linux-media@vger.kernel.org List-Id: devicetree@vger.kernel.org From: Jerry-ch Chen This patch adds nodes for Face Detection (FD) unit. FD is embedded in Mediatek SoCs and works with the co-processor to perform face detection on the input data and image and output detected face result. Signed-off-by: Jerry-ch Chen --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index c3a516e63141..6f31b5f4c17c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -432,6 +432,19 @@ #clock-cells = <1>; }; + fd:fd@1502b000 { + compatible = "mediatek,mt8183-fd"; + mediatek,scp = <&scp>; + iommus = <&iommu M4U_PORT_CAM_FDVT_RP>, + <&iommu M4U_PORT_CAM_FDVT_WR>, + <&iommu M4U_PORT_CAM_FDVT_RB>; + reg = <0 0x1502b000 0 0x1000>; + interrupts = ; + clocks = <&imgsys CLK_IMG_FDVT>; + clock-names = "fd"; + power-domains = <&scpsys MT8183_POWER_DOMAIN_ISP>; + }; + vdecsys: syscon@16000000 { compatible = "mediatek,mt8183-vdecsys", "syscon"; reg = <0 0x16000000 0 0x1000>; -- 2.18.0