From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stephen Boyd Subject: Re: [PATCH 2/2] clk: meson: a1: add support for Amlogic A1 clock driver Date: Wed, 25 Sep 2019 06:12:31 -0700 Message-ID: <20190925131232.4751020640@mail.kernel.org> References: <1569411888-98116-1-git-send-email-jian.hu@amlogic.com> <1569411888-98116-3-git-send-email-jian.hu@amlogic.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Return-path: In-Reply-To: <1569411888-98116-3-git-send-email-jian.hu@amlogic.com> Sender: linux-kernel-owner@vger.kernel.org To: Jerome Brunet , Neil Armstrong Cc: Rob Herring , Jianxin Pan , devicetree@vger.kernel.org, Martin Blumenstingl , Kevin Hilman , Michael Turquette , linux-kernel@vger.kernel.org, Jian Hu , Qiufang Dai , linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org List-Id: devicetree@vger.kernel.org Quoting Jian Hu (2019-09-25 04:44:48) > The Amlogic A1 clock includes three parts: > peripheral clocks, pll clocks, CPU clocks. > sys pll and CPU clocks will be sent in next patch. >=20 > Unlike the previous series, there is no EE/AO domain > in A1 CLK controllers. >=20 > Signed-off-by: Jian Hu > Signed-off-by: Jianxin Pan This second name didn't send the patch. Please follow the signoff procedures documented in Documentation/process/submitting-patches.rst > diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms > index 16d7614..a48f67d 100644 > --- a/arch/arm64/Kconfig.platforms > +++ b/arch/arm64/Kconfig.platforms > @@ -138,6 +138,7 @@ config ARCH_MESON > select COMMON_CLK_AXG > select COMMON_CLK_G12A > select MESON_IRQ_GPIO > + select COMMON_CLK_A1 Sort? > help > This enables support for the arm64 based Amlogic SoCs > such as the s905, S905X/D, S912, A113X/D or S905X/D2 > diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig > index dabeb43..e6cb4c3 100644 > --- a/drivers/clk/meson/Kconfig > +++ b/drivers/clk/meson/Kconfig > @@ -107,3 +107,13 @@ config COMMON_CLK_G12A > help > Support for the clock controller on Amlogic S905D2, S905X2 and = S905Y2 > devices, aka g12a. Say Y if you want peripherals to work. > + > +config COMMON_CLK_A1 Probably should be placed somewhere alphabetically in this file? > + bool > + depends on ARCH_MESON > + select COMMON_CLK_MESON_REGMAP > + select COMMON_CLK_MESON_DUALDIV > + select COMMON_CLK_MESON_PLL > + help > + Support for the clock controller on Amlogic A113L device, > + aka a1. Say Y if you want peripherals to work. > diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile > index 3939f21..6be3a8f 100644 > --- a/drivers/clk/meson/Makefile > +++ b/drivers/clk/meson/Makefile > @@ -19,3 +19,4 @@ obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) +=3D axg-audio.o > obj-$(CONFIG_COMMON_CLK_GXBB) +=3D gxbb.o gxbb-aoclk.o > obj-$(CONFIG_COMMON_CLK_G12A) +=3D g12a.o g12a-aoclk.o > obj-$(CONFIG_COMMON_CLK_MESON8B) +=3D meson8b.o > +obj-$(CONFIG_COMMON_CLK_A1) +=3D a1.o I would guess this should be sorted on Kconfig name in this file? > diff --git a/drivers/clk/meson/a1.c b/drivers/clk/meson/a1.c > new file mode 100644 > index 0000000..26edae0f > --- /dev/null > +++ b/drivers/clk/meson/a1.c > @@ -0,0 +1,2617 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include "clk-mpll.h" > +#include "clk-pll.h" > +#include "clk-regmap.h" > +#include "vid-pll-div.h" > +#include "clk-dualdiv.h" > +#include "meson-eeclk.h" > +#include "a1.h" > + [...] > + > +/* > + * The Meson A1 HIFI PLL is 614.4M, it requires > + * a strict register sequence to enable the PLL. > + * set meson_clk_pcie_pll_ops as its ops Please remove this last line as it's obvious from the code what ops are used. > + */ > +static struct clk_regmap a1_hifi_pll =3D { > + .data =3D &(struct meson_clk_pll_data){ > + .en =3D { > + .reg_off =3D ANACTRL_HIFIPLL_CTRL0, > + .shift =3D 28, > + .width =3D 1, > + }, > + .m =3D { > + .reg_off =3D ANACTRL_HIFIPLL_CTRL0, > + .shift =3D 0, > + .width =3D 8, > + }, > + .n =3D { > + .reg_off =3D ANACTRL_HIFIPLL_CTRL0, > + .shift =3D 10, > + .width =3D 5, > + }, > + .frac =3D { > + .reg_off =3D ANACTRL_HIFIPLL_CTRL1, > + .shift =3D 0, > + .width =3D 19, > + }, > + .l =3D { > + .reg_off =3D ANACTRL_HIFIPLL_STS, > + .shift =3D 31, > + .width =3D 1, > + }, > + .table =3D a1_hifi_pll_params_table, > + .init_regs =3D a1_hifi_init_regs, > + .init_count =3D ARRAY_SIZE(a1_hifi_init_regs), > + }, > + .hw.init =3D &(struct clk_init_data){ > + .name =3D "hifi_pll", > + .ops =3D &meson_clk_pcie_pll_ops, > + .parent_hws =3D (const struct clk_hw *[]) { > + &a1_xtal_hifipll.hw > + }, > + .num_parents =3D 1, > + }, > +}; > + [..] > + > +static struct clk_regmap a1_fclk_div2 =3D { > + .data =3D &(struct clk_regmap_gate_data){ > + .offset =3D ANACTRL_FIXPLL_CTRL0, > + .bit_idx =3D 21, > + }, > + .hw.init =3D &(struct clk_init_data){ > + .name =3D "fclk_div2", > + .ops =3D &clk_regmap_gate_ops, > + .parent_hws =3D (const struct clk_hw *[]) { > + &a1_fclk_div2_div.hw > + }, > + .num_parents =3D 1, > + /* > + * add CLK_IS_CRITICAL flag to avoid being disabled by cl= k core > + * or its children clocks. This comment is useless. Please replace it with an actual reason for keeping the clk on instead of describing what the flag does. > + */ > + .flags =3D CLK_IS_CRITICAL, > + }, > +}; > + [..] > +static struct clk_regmap a1_dmc =3D { > + .data =3D &(struct clk_regmap_gate_data){ > + .offset =3D DMC_CLK_CTRL, > + .bit_idx =3D 8, > + }, > + .hw.init =3D &(struct clk_init_data) { > + .name =3D "dmc", > + .ops =3D &clk_regmap_gate_ops, > + .parent_hws =3D (const struct clk_hw *[]) { > + &a1_dmc_sel2.hw > + }, > + .num_parents =3D 1, > + /* > + * add CLK_IGNORE_UNUSED to avoid hangup > + * DDR clock should not change at runtime > + */ > + .flags =3D CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, So not CLK_IS_CRITICAL? > + }, > +}; > + [...] > + > +/* > + * cpu clock register base address is 0xfd000080 > + */ > +static struct clk_regmap *const a1_cpu_clk_regmaps[] =3D { > + /* TODO */ Can it be done? > +};