From mboxrd@z Thu Jan 1 00:00:00 1970 From: Krzysztof Kozlowski Subject: Re: [PATCH 1/3] ARM: dts: exynos: Add interrupt to DMC controller in Exynos5422 Date: Fri, 27 Sep 2019 10:53:59 +0200 Message-ID: <20190927085359.GA19131@pi3> References: <20190925161813.21117-1-l.luba@partner.samsung.com> <20190925161813.21117-2-l.luba@partner.samsung.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Return-path: Content-Disposition: inline In-Reply-To: <20190925161813.21117-2-l.luba@partner.samsung.com> Sender: linux-kernel-owner@vger.kernel.org To: Lukasz Luba Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, b.zolnierkie@samsung.com, kgene@kernel.org, mark.rutland@arm.com, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, robh+dt@kernel.org, willy.mh.wolff.ml@gmail.com List-Id: devicetree@vger.kernel.org On Wed, Sep 25, 2019 at 06:18:11PM +0200, Lukasz Luba wrote: > Add interrupt to Dynamic Memory Controller in Exynos5422 and Odroid > XU3-family boards. It will be used instead of devfreq polling mode > governor. The interrupt is connected to performance counters private > for DMC, which might track utilisation of the memory channels. > > Signed-off-by: Lukasz Luba > --- > arch/arm/boot/dts/exynos5420.dtsi | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi > index ac49373baae7..72738e620d11 100644 > --- a/arch/arm/boot/dts/exynos5420.dtsi > +++ b/arch/arm/boot/dts/exynos5420.dtsi > @@ -240,6 +240,8 @@ > dmc: memory-controller@10c20000 { > compatible = "samsung,exynos5422-dmc"; > reg = <0x10c20000 0x100>, <0x10c30000 0x100>; > + interrupt-parent = <&combiner>; > + interrupts = <16 0>; You register DMC for DREX0 and DREX1 but take only DREX0 interrupt. Why skipping second? Best regards, Krzysztof > clocks = <&clock CLK_FOUT_SPLL>, > <&clock CLK_MOUT_SCLK_SPLL>, > <&clock CLK_FF_DOUT_SPLL2>, > -- > 2.17.1 >