From: Shawn Guo <shawnguo@kernel.org>
To: Wen He <wen.he_1@nxp.com>
Cc: linux-devel@linux.nxdi.nxp.com, Li Yang <leoyang.li@nxp.com>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [v2 1/2] arm64: dts: ls1028a: Update the clock providers for the Mali DP500
Date: Mon, 14 Oct 2019 14:19:31 +0800 [thread overview]
Message-ID: <20191014061930.GB12262@dragon> (raw)
In-Reply-To: <20190920083419.5092-1-wen.he_1@nxp.com>
On Fri, Sep 20, 2019 at 04:34:18PM +0800, Wen He wrote:
> In order to maximise performance of the LCD Controller's 64-bit AXI
> bus, for any give speed bin of the device, the AXI master interface
> clock(ACLK) clock can be up to CPU_frequency/2, which is already
> capable of optimal performance. In general, ACLK is always expected
> to be equal to CPU_frequency/2. APB slave interface clock(PCLK) and
> Main processing clock(PCLK) both are tied to the same clock as ACLK.
>
> This change followed the LS1028A Architecture Specification Manual.
>
> Signed-off-by: Wen He <wen.he_1@nxp.com>
Applied, thanks.
prev parent reply other threads:[~2019-10-14 6:19 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-20 8:34 [v2 1/2] arm64: dts: ls1028a: Update the clock providers for the Mali DP500 Wen He
2019-09-20 8:34 ` [v2 2/2] arm64: dts: ls1028a: Update the DT node definition for dpclk Wen He
2019-10-07 12:35 ` Shawn Guo
2019-10-08 4:08 ` [EXT] " Wen He
2019-10-14 6:21 ` Shawn Guo
2019-10-14 6:25 ` Wen He
2019-10-07 12:32 ` [v2 1/2] arm64: dts: ls1028a: Update the clock providers for the Mali DP500 Shawn Guo
2019-10-07 21:29 ` Leo Li
2019-10-14 6:19 ` Shawn Guo [this message]
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