From mboxrd@z Thu Jan 1 00:00:00 1970 From: Shawn Guo Subject: Re: [v2 1/2] arm64: dts: ls1028a: Update the clock providers for the Mali DP500 Date: Mon, 14 Oct 2019 14:19:31 +0800 Message-ID: <20191014061930.GB12262@dragon> References: <20190920083419.5092-1-wen.he_1@nxp.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: <20190920083419.5092-1-wen.he_1@nxp.com> Sender: linux-kernel-owner@vger.kernel.org To: Wen He Cc: linux-devel@linux.nxdi.nxp.com, Li Yang , Rob Herring , Mark Rutland , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org List-Id: devicetree@vger.kernel.org On Fri, Sep 20, 2019 at 04:34:18PM +0800, Wen He wrote: > In order to maximise performance of the LCD Controller's 64-bit AXI > bus, for any give speed bin of the device, the AXI master interface > clock(ACLK) clock can be up to CPU_frequency/2, which is already > capable of optimal performance. In general, ACLK is always expected > to be equal to CPU_frequency/2. APB slave interface clock(PCLK) and > Main processing clock(PCLK) both are tied to the same clock as ACLK. > > This change followed the LS1028A Architecture Specification Manual. > > Signed-off-by: Wen He Applied, thanks.