From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.6 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6E3B6CA9EAF for ; Thu, 24 Oct 2019 19:03:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3EE6121929 for ; Thu, 24 Oct 2019 19:03:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1571943799; bh=ePbGhKrM0X2X47Ig0cCqNbkm6vptO7VyM2yJnt4HOIA=; h=Date:From:To:Cc:Subject:References:In-Reply-To:List-ID:From; b=qSz+Ff6VEkBbBtM1asrFv1Pj9gLU2GPel5/bw5+v3VSOuuzUmUQwIOBGGqvdrcoch YwIMOCHdHc6SiUX5okVSu4HQqh1wGXMjCY60fvUOoHPE2hX4rXLDZng8ojZR+DKFfC bc7iOdvmok/CwHhMMSsTWuac+AW2s/HuIeT5zS8g= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2392263AbfJXTDS (ORCPT ); Thu, 24 Oct 2019 15:03:18 -0400 Received: from mail.kernel.org ([198.145.29.99]:42680 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2391577AbfJXTDS (ORCPT ); Thu, 24 Oct 2019 15:03:18 -0400 Received: from localhost (unknown [109.190.253.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id EBE492070B; Thu, 24 Oct 2019 19:03:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1571943797; bh=ePbGhKrM0X2X47Ig0cCqNbkm6vptO7VyM2yJnt4HOIA=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=RtSj9ZsU+Qi/+k4LBe1ymBcSWx41hn33zdDT0kZRVK/BKRx2NjzZaugw+m+Ax7OgR 1of8SxMH/iJeyGtG2GxLaBGjUnkI9tRXqPBq3sj8s9batNIfLycusnajxA8I1HUfEF l9r+xiRzlYUv7fKlZKX/QOAKdLIBdxgGFsrUltjA= Date: Thu, 24 Oct 2019 20:27:49 +0200 From: Maxime Ripard To: Jagan Teki Cc: Chen-Yu Tsai , David Airlie , Daniel Vetter , Rob Herring , Mark Rutland , Michael Trimarchi , Icenowy Zheng , linux-sunxi , dri-devel , linux-arm-kernel , linux-kernel , devicetree Subject: Re: [PATCH v10 5/6] arm64: dts: allwinner: a64: Add MIPI DSI pipeline Message-ID: <20191024182749.czihj3gnvj5yz2eo@hendrix> References: <20191005141913.22020-1-jagan@amarulasolutions.com> <20191005141913.22020-6-jagan@amarulasolutions.com> <20191007105708.raxavxk4n7bvxh7x@gilmour> <20191016080306.44pmo3rfmtnkgosq@gilmour> <20191017095225.ntx647ivegaldlyf@gilmour> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: NeoMutt/20180716 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Thu, Oct 24, 2019 at 01:28:28PM +0530, Jagan Teki wrote: > On Thu, Oct 17, 2019 at 3:22 PM Maxime Ripard wrote: > > > > On Wed, Oct 16, 2019 at 02:19:44PM +0530, Jagan Teki wrote: > > > On Wed, Oct 16, 2019 at 1:33 PM Maxime Ripard wrote: > > > > > > > > On Mon, Oct 14, 2019 at 05:37:50PM +0530, Jagan Teki wrote: > > > > > On Mon, Oct 7, 2019 at 4:27 PM Maxime Ripard wrote: > > > > > > > > > > > > On Sat, Oct 05, 2019 at 07:49:12PM +0530, Jagan Teki wrote: > > > > > > > Add MIPI DSI pipeline for Allwinner A64. > > > > > > > > > > > > > > - dsi node, with A64 compatible since it doesn't support > > > > > > > DSI_SCLK gating unlike A33 > > > > > > > - dphy node, with A64 compatible with A33 fallback since > > > > > > > DPHY on A64 and A33 is similar > > > > > > > - finally, attach the dsi_in to tcon0 for complete MIPI DSI > > > > > > > > > > > > > > Signed-off-by: Jagan Teki > > > > > > > Tested-by: Merlijn Wajer > > > > > > > --- > > > > > > > arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 38 +++++++++++++++++++ > > > > > > > 1 file changed, 38 insertions(+) > > > > > > > > > > > > > > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi > > > > > > > index 69128a6dfc46..ad4170b8aee0 100644 > > > > > > > --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi > > > > > > > +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi > > > > > > > @@ -382,6 +382,12 @@ > > > > > > > #address-cells = <1>; > > > > > > > #size-cells = <0>; > > > > > > > reg = <1>; > > > > > > > + > > > > > > > + tcon0_out_dsi: endpoint@1 { > > > > > > > + reg = <1>; > > > > > > > + remote-endpoint = <&dsi_in_tcon0>; > > > > > > > + allwinner,tcon-channel = <1>; > > > > > > > + }; > > > > > > > }; > > > > > > > }; > > > > > > > }; > > > > > > > @@ -1003,6 +1009,38 @@ > > > > > > > status = "disabled"; > > > > > > > }; > > > > > > > > > > > > > > + dsi: dsi@1ca0000 { > > > > > > > + compatible = "allwinner,sun50i-a64-mipi-dsi"; > > > > > > > + reg = <0x01ca0000 0x1000>; > > > > > > > + interrupts = ; > > > > > > > + clocks = <&ccu CLK_BUS_MIPI_DSI>; > > > > > > > + clock-names = "bus"; > > > > > > > > > > > > This won't validate with the bindings you have either here, since it > > > > > > still expects bus and mod. > > > > > > > > > > > > I guess in that cas, we can just drop clock-names, which will require > > > > > > a bit of work on the driver side as well. > > > > > > > > > > Okay. > > > > > mod clock is not required for a64, ie reason we have has_mod_clk quirk > > > > > patch. Adjust the clock-names: on dt-bindings would make sense here, > > > > > what do you think? > > > > > > > > I'm confused, what are you suggesting? > > > > > > Sorry for the confusion. > > > > > > The mod clock is not required for A64 and we have a patch for handling > > > mod clock using has_mod_clk quirk(on the series), indeed the mod clock > > > is available in A31 and not needed for A64. So, to satisfy this > > > requirement the clock-names on dt-bindings can update to make mod > > > clock-name is optional and bus clock is required. > > > > No, the bus clock name is not needed if there's only one clock. > > Okay, is it because the same clock handle it on PHY side? No, because there's only one clock and thus you don't need to differentiate them. > > > > > I'm not exactly sure, this is correct but trying to understand if it > > > is possible or not? something like > > > > > > clocks: > > > minItems: 1 > > > maxItems: 2 > > > items: > > > - description: Bus Clock > > > - description: Module Clock > > > > That's correct. > > > > > clock-names: > > > minItems: 1 > > > maxItems: 2 > > > items: > > > - const: bus > > > - const: mod > > > > Here, just keep the current clock-names definition, and make it > > required only for SoCs that are not the A64 > > Okay, please have a look here I have pasted the diff for comments. > > clocks: > + minItems: 2 > items: > - description: Bus Clock > - description: Module Clock Didn't you tell me that you didn't need the module clock? How do you handle the case were you just have the bus clock then? Maxime