* Re: [PATCH 1/5] arm64: dts: imx8qxp: Move usdhc clocks assignment to board DT
[not found] <1571192067-19600-1-git-send-email-Anson.Huang@nxp.com>
@ 2019-10-20 14:35 ` Abel Vesa
2019-10-26 12:09 ` Shawn Guo
1 sibling, 0 replies; 4+ messages in thread
From: Abel Vesa @ 2019-10-20 14:35 UTC (permalink / raw)
To: Anson Huang
Cc: robh+dt@kernel.org, mark.rutland@arm.com, shawnguo@kernel.org,
s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com,
Jun Li, Jacky Bai, Daniel Baluta, Leonard Crestez,
daniel.lezcano@linaro.org, l.stach@pengutronix.de,
ccaione@baylibre.com, andrew.smirnov@gmail.com, jon@solid-run.com,
baruch@tkos.co.il, angus@akkea.ca, pavel@ucw.cz, agx@sigxcpu.org,
Troy Kisky, Gary Bisson, dafna.hirschfeld@collabora.com,
Richard Hu, andradanciu1997@gmail.com,
manivannan.sadhasivam@linaro.org, Aisheng Dong, Peng Fan,
Andy Duan, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, dl-linux-imx
On 19-10-16 10:14:23, Anson Huang wrote:
> usdhc's clock rate is different according to different devices
> connected, so clock rate assignment should be placed in board
> DT according to different devices connected on each usdhc port.
>
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
For the entire patchset:
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
> ---
> arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts | 4 ++++
> arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 4 ++++
> arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 6 ------
> 3 files changed, 8 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts b/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts
> index 91eef97..a3f8cf1 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts
> @@ -133,6 +133,8 @@
> &usdhc1 {
> #address-cells = <1>;
> #size-cells = <0>;
> + assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>;
> + assigned-clock-rates = <200000000>;
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_usdhc1>;
> bus-width = <4>;
> @@ -149,6 +151,8 @@
>
> /* SD */
> &usdhc2 {
> + assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>;
> + assigned-clock-rates = <200000000>;
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_usdhc2>;
> bus-width = <4>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
> index 88dd9132..d3d26cc 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
> @@ -137,6 +137,8 @@
> };
>
> &usdhc1 {
> + assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>;
> + assigned-clock-rates = <200000000>;
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_usdhc1>;
> bus-width = <8>;
> @@ -147,6 +149,8 @@
> };
>
> &usdhc2 {
> + assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>;
> + assigned-clock-rates = <200000000>;
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_usdhc2>;
> bus-width = <4>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> index 2d69f1a..9646a41 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> @@ -368,8 +368,6 @@
> <&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>,
> <&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>;
> clock-names = "ipg", "per", "ahb";
> - assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>;
> - assigned-clock-rates = <200000000>;
> power-domains = <&pd IMX_SC_R_SDHC_0>;
> status = "disabled";
> };
> @@ -383,8 +381,6 @@
> <&conn_lpcg IMX_CONN_LPCG_SDHC1_PER_CLK>,
> <&conn_lpcg IMX_CONN_LPCG_SDHC1_HCLK>;
> clock-names = "ipg", "per", "ahb";
> - assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>;
> - assigned-clock-rates = <200000000>;
> power-domains = <&pd IMX_SC_R_SDHC_1>;
> fsl,tuning-start-tap = <20>;
> fsl,tuning-step= <2>;
> @@ -400,8 +396,6 @@
> <&conn_lpcg IMX_CONN_LPCG_SDHC2_PER_CLK>,
> <&conn_lpcg IMX_CONN_LPCG_SDHC2_HCLK>;
> clock-names = "ipg", "per", "ahb";
> - assigned-clocks = <&clk IMX_CONN_SDHC2_CLK>;
> - assigned-clock-rates = <200000000>;
> power-domains = <&pd IMX_SC_R_SDHC_2>;
> status = "disabled";
> };
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 1/5] arm64: dts: imx8qxp: Move usdhc clocks assignment to board DT
[not found] <1571192067-19600-1-git-send-email-Anson.Huang@nxp.com>
2019-10-20 14:35 ` [PATCH 1/5] arm64: dts: imx8qxp: Move usdhc clocks assignment to board DT Abel Vesa
@ 2019-10-26 12:09 ` Shawn Guo
2019-10-28 1:29 ` Anson Huang
1 sibling, 1 reply; 4+ messages in thread
From: Shawn Guo @ 2019-10-26 12:09 UTC (permalink / raw)
To: Anson Huang
Cc: robh+dt, mark.rutland, s.hauer, kernel, festevam, jun.li,
ping.bai, daniel.baluta, leonard.crestez, daniel.lezcano, l.stach,
ccaione, abel.vesa, andrew.smirnov, jon, baruch, angus, pavel,
agx, troy.kisky, gary.bisson, dafna.hirschfeld, richard.hu,
andradanciu1997, manivannan.sadhasivam, aisheng.dong, peng.fan,
fugang.duan, devicetree, linux-arm-kernel, linux-kernel,
Linux-imx
On Wed, Oct 16, 2019 at 10:14:23AM +0800, Anson Huang wrote:
> usdhc's clock rate is different according to different devices
> connected, so clock rate assignment should be placed in board
> DT according to different devices connected on each usdhc port.
I think it should be fine that we have a reasonable default settings in
soc.dtsi, and boards that need a different setup can overwrite the
settings in board.dts.
Shawn
>
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> ---
> arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts | 4 ++++
> arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 4 ++++
> arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 6 ------
> 3 files changed, 8 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts b/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts
> index 91eef97..a3f8cf1 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts
> @@ -133,6 +133,8 @@
> &usdhc1 {
> #address-cells = <1>;
> #size-cells = <0>;
> + assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>;
> + assigned-clock-rates = <200000000>;
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_usdhc1>;
> bus-width = <4>;
> @@ -149,6 +151,8 @@
>
> /* SD */
> &usdhc2 {
> + assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>;
> + assigned-clock-rates = <200000000>;
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_usdhc2>;
> bus-width = <4>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
> index 88dd9132..d3d26cc 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
> @@ -137,6 +137,8 @@
> };
>
> &usdhc1 {
> + assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>;
> + assigned-clock-rates = <200000000>;
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_usdhc1>;
> bus-width = <8>;
> @@ -147,6 +149,8 @@
> };
>
> &usdhc2 {
> + assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>;
> + assigned-clock-rates = <200000000>;
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_usdhc2>;
> bus-width = <4>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> index 2d69f1a..9646a41 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> @@ -368,8 +368,6 @@
> <&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>,
> <&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>;
> clock-names = "ipg", "per", "ahb";
> - assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>;
> - assigned-clock-rates = <200000000>;
> power-domains = <&pd IMX_SC_R_SDHC_0>;
> status = "disabled";
> };
> @@ -383,8 +381,6 @@
> <&conn_lpcg IMX_CONN_LPCG_SDHC1_PER_CLK>,
> <&conn_lpcg IMX_CONN_LPCG_SDHC1_HCLK>;
> clock-names = "ipg", "per", "ahb";
> - assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>;
> - assigned-clock-rates = <200000000>;
> power-domains = <&pd IMX_SC_R_SDHC_1>;
> fsl,tuning-start-tap = <20>;
> fsl,tuning-step= <2>;
> @@ -400,8 +396,6 @@
> <&conn_lpcg IMX_CONN_LPCG_SDHC2_PER_CLK>,
> <&conn_lpcg IMX_CONN_LPCG_SDHC2_HCLK>;
> clock-names = "ipg", "per", "ahb";
> - assigned-clocks = <&clk IMX_CONN_SDHC2_CLK>;
> - assigned-clock-rates = <200000000>;
> power-domains = <&pd IMX_SC_R_SDHC_2>;
> status = "disabled";
> };
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* RE: [PATCH 1/5] arm64: dts: imx8qxp: Move usdhc clocks assignment to board DT
2019-10-26 12:09 ` Shawn Guo
@ 2019-10-28 1:29 ` Anson Huang
2019-10-28 3:15 ` Shawn Guo
0 siblings, 1 reply; 4+ messages in thread
From: Anson Huang @ 2019-10-28 1:29 UTC (permalink / raw)
To: Shawn Guo
Cc: robh+dt@kernel.org, mark.rutland@arm.com, s.hauer@pengutronix.de,
kernel@pengutronix.de, festevam@gmail.com, Jun Li, Jacky Bai,
Daniel Baluta, Leonard Crestez, daniel.lezcano@linaro.org,
l.stach@pengutronix.de, ccaione@baylibre.com, Abel Vesa,
andrew.smirnov@gmail.com, jon@solid-run.com, baruch@tkos.co.il,
angus@akkea.ca, pavel@ucw.cz, agx@sigxcpu.org, Troy Kisky,
Gary Bisson, dafna.hirschfeld@collabora.com, Richard Hu,
andradanciu1997@gmail.com, manivannan.sadhasivam@linaro.org,
Aisheng Dong, Peng Fan, Andy Duan, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, dl-linux-imx
Hi, Shawn
> On Wed, Oct 16, 2019 at 10:14:23AM +0800, Anson Huang wrote:
> > usdhc's clock rate is different according to different devices
> > connected, so clock rate assignment should be placed in board DT
> > according to different devices connected on each usdhc port.
>
> I think it should be fine that we have a reasonable default settings in soc.dtsi,
> and boards that need a different setup can overwrite the settings in
> board.dts.
Someone was complaining about the usdhc clock assignment in soc.dtsi, because some
usdhc nodes are having clock assignments while some are NOT. That is why I did this
patch set. I agree that we can have default settings in soc.dtsi, so do you think it makes
sense to add default clock assignment to all usdhc nodes? If yes, I will redo the patch
set.
Thanks,
Anson.
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 1/5] arm64: dts: imx8qxp: Move usdhc clocks assignment to board DT
2019-10-28 1:29 ` Anson Huang
@ 2019-10-28 3:15 ` Shawn Guo
0 siblings, 0 replies; 4+ messages in thread
From: Shawn Guo @ 2019-10-28 3:15 UTC (permalink / raw)
To: Anson Huang
Cc: robh+dt@kernel.org, mark.rutland@arm.com, s.hauer@pengutronix.de,
kernel@pengutronix.de, festevam@gmail.com, Jun Li, Jacky Bai,
Daniel Baluta, Leonard Crestez, daniel.lezcano@linaro.org,
l.stach@pengutronix.de, ccaione@baylibre.com, Abel Vesa,
andrew.smirnov@gmail.com, jon@solid-run.com, baruch@tkos.co.il,
angus@akkea.ca, pavel@ucw.cz, agx@sigxcpu.org, Troy Kisky,
Gary Bisson, dafna.hirschfeld@collabora.com, Richard Hu,
andradanciu1997@gmail.com, manivannan.sadhasivam@linaro.org,
Aisheng Dong, Peng Fan, Andy Duan, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, dl-linux-imx
On Mon, Oct 28, 2019 at 01:29:32AM +0000, Anson Huang wrote:
> Hi, Shawn
>
> > On Wed, Oct 16, 2019 at 10:14:23AM +0800, Anson Huang wrote:
> > > usdhc's clock rate is different according to different devices
> > > connected, so clock rate assignment should be placed in board DT
> > > according to different devices connected on each usdhc port.
> >
> > I think it should be fine that we have a reasonable default settings in soc.dtsi,
> > and boards that need a different setup can overwrite the settings in
> > board.dts.
>
> Someone was complaining about the usdhc clock assignment in soc.dtsi, because some
> usdhc nodes are having clock assignments while some are NOT. That is why I did this
> patch set. I agree that we can have default settings in soc.dtsi, so do you think it makes
> sense to add default clock assignment to all usdhc nodes? If yes, I will redo the patch
> set.
I had a second thought on this. To ease the maintenance of soc.dtsi,
let's do clock assignments in board.dts.
Series applied, thanks.
Shawn
^ permalink raw reply [flat|nested] 4+ messages in thread
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2019-10-20 14:35 ` [PATCH 1/5] arm64: dts: imx8qxp: Move usdhc clocks assignment to board DT Abel Vesa
2019-10-26 12:09 ` Shawn Guo
2019-10-28 1:29 ` Anson Huang
2019-10-28 3:15 ` Shawn Guo
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