From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.9 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 99B3ECA9EBC for ; Mon, 28 Oct 2019 10:22:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 639D020578 for ; Mon, 28 Oct 2019 10:22:05 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="TIV3wE0u" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388103AbfJ1KWF (ORCPT ); Mon, 28 Oct 2019 06:22:05 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:55922 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732186AbfJ1KWE (ORCPT ); Mon, 28 Oct 2019 06:22:04 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x9SAM2S4127050; Mon, 28 Oct 2019 05:22:02 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1572258122; bh=PPfmQTQzpjZI6/syLNanL8WvNYmx/cljQMHzTOzXfpA=; h=From:To:CC:Subject:Date; b=TIV3wE0uT34tziVChKbsEgDxQ8VOPBC7hAMwuhs7/ZO/sP38RBaURle1ME0Xes7Ct jcEQdxExRq74sM8Wa9xtifId2e/oRHqyDkd543ZbnETd0Pgdw+BrIGS6Y3h5xc01Uz sJ9vZ/rN/zmlyDASuMdo4dEY7AUzgLi6HEuQgixU= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x9SAM2nC003812 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 28 Oct 2019 05:22:02 -0500 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 28 Oct 2019 05:21:49 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Mon, 28 Oct 2019 05:22:01 -0500 Received: from lta0400828a.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x9SALwqF024783; Mon, 28 Oct 2019 05:21:59 -0500 From: Roger Quadros To: CC: , , , , , , Roger Quadros Subject: [PATCH v4 0/3] phy: cadence: j721e-wiz: Add Type-C plug flip support Date: Mon, 28 Oct 2019 12:21:50 +0200 Message-ID: <20191028102153.24866-1-rogerq@ti.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi, On J721e platform, the 2 lanes of SERDES PHY are used to achieve USB Type-C plug flip support without any additional MUX component by using a lane swap feature. However, the driver needs to know the Type-C plug orientation before it can decide whether to swap the lanes or not. This is achieved via a GPIO named DIR. Another constraint is that the lane swap must happen only when the PHY is in inactive state. This is achieved by sampling the GPIO and programming the lane swap before bringing the PHY out of reset. This series adds support to read the GPIO and accordingly program the Lane swap for Type-C plug flip support. Series must be applied on top of https://lkml.org/lkml/2019/10/23/589 cheers, -roger Changelog: v4 - fixes in dt-binding document - fix typo - change to typec-dir-debounce-ms and add min/max/default values - drop reference to uint32 type - fixes in driver - change to updated typec-dir-debounce-ms property - add limit checks and use default value if not specified v3 - Rebase on v2 of PHY series and update DT binding to yaml v2 - revise commit log of patch 1 - use regmap_field in patch 3 Roger Quadros (3): phy: cadence: Sierra: add phy_reset hook dt-bindings: phy: ti,phy-j721e-wiz: Add Type-C dir GPIO phy: ti: j721e-wiz: Manage typec-gpio-dir .../bindings/phy/ti,phy-j721e-wiz.yaml | 17 ++++++ drivers/phy/cadence/phy-cadence-sierra.c | 10 +++ drivers/phy/ti/phy-j721e-wiz.c | 61 +++++++++++++++++++ 3 files changed, 88 insertions(+) -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki