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[46.91.226.206]) by smtp.gmail.com with ESMTPSA id u1sm20356221wru.90.2019.10.29.06.02.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Oct 2019 06:02:24 -0700 (PDT) Date: Tue, 29 Oct 2019 14:02:22 +0100 From: Thierry Reding To: Dmitry Osipenko Cc: Rob Herring , Peter De Schrijver , Jonathan Hunter , Mark Brown , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 0/3] Support regulators coupling on NVIDIA Tegra20/30 Message-ID: <20191029130222.GA508460@ulmo> References: <20190725151832.9802-1-digetx@gmail.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="1yeeQ81UyVL57Vl7" Content-Disposition: inline In-Reply-To: <20190725151832.9802-1-digetx@gmail.com> User-Agent: Mutt/1.12.2 (2019-09-21) Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org --1yeeQ81UyVL57Vl7 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Thu, Jul 25, 2019 at 06:18:29PM +0300, Dmitry Osipenko wrote: > Hello, >=20 > The voltage regulators need to be coupled on NVIDIA Tegra20 and Tegra30 > SoCs in order to provide voltage scaling functionality in a generic way. > All necessary regulator-core patches that added support for the regulators > coupling are already have been merge into mainline kernel. This series > adds customized voltage couplers for Tegra20/30 SoCs, paving the way for > a refined CPUFreq driver that will utilize voltage scaling and other neat > features. This is a resend of a leftover patches from a previous series > [1] that was partially applied by Mark Brown. Please review, thanks in > advance! >=20 > [1] https://patchwork.ozlabs.org/project/linux-tegra/list/?series=3D115626 >=20 > Changelog: >=20 > v2: - Some days ago OPP framework got a change that makes CPU regulator > to be enabled at the time of CPUFreq's driver initializing OPPs. > In a result the CPU's voltage is dropped to a minimum value on > CPUFreq's setting up because there are no consumers at the time > of regulator's enabling, thus CPU is getting into a big trouble. > This problem is now resolved in the couplers code by assuming > that min_uV=3Dcurrent_uV for CPU's regulator if it doesn't have > any active consumers. >=20 > Dmitry Osipenko (3): > dt-bindings: regulator: Document regulators coupling of NVIDIA > Tegra20/30 SoCs > soc/tegra: regulators: Add regulators coupler for Tegra20 > soc/tegra: regulators: Add regulators coupler for Tegra30 All three patches applied, thanks. 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