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[24.155.109.49]) by smtp.gmail.com with ESMTPSA id o22sm4619317otk.47.2019.10.29.08.48.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Oct 2019 08:48:43 -0700 (PDT) Date: Tue, 29 Oct 2019 10:48:42 -0500 From: Rob Herring To: "Ramuthevar,Vadivel MuruganX" Cc: kishon@ti.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, andriy.shevchenko@intel.com, cheol.yong.kim@intel.com, qi-ming.wu@intel.com, peter.harliman.liem@intel.com Subject: Re: [PATCH v6 1/2] dt-bindings: phy: intel-emmc-phy: Add YAML schema for LGM eMMC PHY Message-ID: <20191029154842.GA3526@bogus> References: <20191021095436.50303-1-vadivel.muruganx.ramuthevar@linux.intel.com> <20191021095436.50303-2-vadivel.muruganx.ramuthevar@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20191021095436.50303-2-vadivel.muruganx.ramuthevar@linux.intel.com> User-Agent: Mutt/1.10.1 (2018-07-13) Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Mon, Oct 21, 2019 at 05:54:35PM +0800, Ramuthevar,Vadivel MuruganX wrote: > From: Ramuthevar Vadivel Murugan > > Add a YAML schema to use the host controller driver with the > eMMC PHY on Intel's Lightning Mountain SoC. > > Signed-off-by: Ramuthevar Vadivel Murugan > --- > --- > .../bindings/phy/intel,lgm-emmc-phy.yaml | 63 ++++++++++++++++++++++ > 1 file changed, 63 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/intel,lgm-emmc-phy.yaml > > diff --git a/Documentation/devicetree/bindings/phy/intel,lgm-emmc-phy.yaml b/Documentation/devicetree/bindings/phy/intel,lgm-emmc-phy.yaml > new file mode 100644 > index 000000000000..bc1285be31f9 > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/intel,lgm-emmc-phy.yaml > @@ -0,0 +1,63 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/intel,lgm-emmc-phy.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Intel Lightning Mountain(LGM) eMMC PHY Device Tree Bindings > + > +maintainers: > + - Ramuthevar Vadivel Murugan > + > +description: Bindings for eMMC PHY on Intel's Lightning Mountain SoC, syscon > + node is used to reference the base address of eMMC phy registers. > + > +select: You don't need a 'select'. > + properties: > + compatible: > + items: > + - const: intel,lgm-syscon > + - const: intel,lgm-emmc-phy This is not right. You are saying 'compatible' must be: compatible = "intel,lgm-syscon", "intel,lgm-emmc-phy"; > + > + reg: > + maxItems: 1 > + > + required: > + - compatible > + - reg > + > +properties: > + "#phy-cells": > + const: 0 > + > + reg: > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + > + clock-names: > + maxItems: 1 > + > +required: > + - "#phy-cells" > + - compatible > + - reg > + - clocks > + - clock-names > + > +examples: > + - | > + sysconf: chiptop@e0200000 { > + compatible = "intel,lgm-syscon"; > + reg = <0xe0200000 0x100>; > + > + emmc-phy: emmc-phy { phy@a8 What else in in the chiptop block? > + compatible = "intel,lgm-emmc-phy"; > + reg = <0x00a8 0x10>; > + clocks = <&emmc>; > + clock-names = "emmcclk"; > + #phy-cells = <0>; > + }; > + }; > +... > -- > 2.11.0 >