[PATCH 1/3] dt-bindings: net: phy: Add reg-init property

[Michael Walle <michael@walle.cc>]

Describe the reg-init property to configure PHY registers.

Signed-off-by: Michael Walle <michael@walle.cc>
---
 .../devicetree/bindings/net/ethernet-phy.yaml | 31 +++++++++++++++++++
 MAINTAINERS                                   |  1 +
 include/dt-bindings/net/phy.h                 | 18 +++++++++++
 3 files changed, 50 insertions(+)
 create mode 100644 include/dt-bindings/net/phy.h

diff --git a/Documentation/devicetree/bindings/net/ethernet-phy.yaml b/Documentation/devicetree/bindings/net/ethernet-phy.yaml
index f70f18ff821f..d2dda1f33119 100644
--- a/Documentation/devicetree/bindings/net/ethernet-phy.yaml
+++ b/Documentation/devicetree/bindings/net/ethernet-phy.yaml
@@ -153,6 +153,28 @@ properties:
       Delay after the reset was deasserted in microseconds. If
       this property is missing the delay will be skipped.
 
+  reg-init:
+    allOf:
+      - $ref: /schemas/types.yaml#/definitions/uint32-matrix
+        items:
+          items:
+            - description:
+                Set this to zero to write clause-22 register.
+                Set the page ORed with PHY_REG_PAGE to write to
+                a paged register. Set to devad ORed with
+                PHY_REG_C45 to write a clause-45 register.
+            - description:
+                The PHY register.
+            - description:
+                Mask, if non-zero, ANDed with existing register
+                value.
+            - description:
+                Value, ORed with the masked value and written to
+                the register.
+    description:
+      A list of <page_or_devad reg mask value> tuples to configure
+      the PHY registers at startup.
+
 required:
   - reg
 
@@ -173,5 +195,14 @@ examples:
             reset-gpios = <&gpio1 4 1>;
             reset-assert-us = <1000>;
             reset-deassert-us = <2000>;
+
+            reg-init =
+                /* Fix RX and TX clock transition timing */
+                <(PHY_REG_PAGE | 2) 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */
+                /* Adjust LED drive. */
+                <(PHY_REG_PAGE | 3) 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
+                /* irq, blink-activity, blink-link */
+                <(PHY_REG_PAGE | 3) 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
+
         };
     };
diff --git a/MAINTAINERS b/MAINTAINERS
index a69e6db80c79..493ea5e13c2c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6147,6 +6147,7 @@ F:	Documentation/networking/phy.rst
 F:	drivers/net/phy/
 F:	drivers/of/of_mdio.c
 F:	drivers/of/of_net.c
+F:	include/dt-bindings/net/phy.h
 F:	include/linux/*mdio*.h
 F:	include/linux/of_net.h
 F:	include/linux/phy.h
diff --git a/include/dt-bindings/net/phy.h b/include/dt-bindings/net/phy.h
new file mode 100644
index 000000000000..b37853144719
--- /dev/null
+++ b/include/dt-bindings/net/phy.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Device Tree constants for a generic network PHY
+ *
+ * Author: Michael Walle <michael@walle.cc>
+ *
+ */
+
+#ifndef _DT_BINDINGS_NET_PHY_H
+#define _DT_BINDINGS_NET_PHY_H
+
+/* PHY write selection bits */
+
+#define PHY_REG_C22	(0)
+#define PHY_REG_PAGE	(1 << 31)
+#define PHY_REG_C45	(1 << 30)
+
+#endif /* _DT_BINDINGS_NET_PHY_H */
-- 
2.20.1