From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 79134C17440 for ; Tue, 12 Nov 2019 14:25:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5283B222CB for ; Tue, 12 Nov 2019 14:25:41 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="N92YWeJx" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727298AbfKLOZE (ORCPT ); Tue, 12 Nov 2019 09:25:04 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:40490 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727616AbfKLOZE (ORCPT ); Tue, 12 Nov 2019 09:25:04 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id xACEOxOd044422; Tue, 12 Nov 2019 08:24:59 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1573568699; bh=AhKW4zr3y6EnszWY1v1ZvsH1fjzX055dXtF+Ryq9cP0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=N92YWeJxyXEYlijNwHxHC2WWGgC9SRKA+K1B0m5VGk3l92b+/sxVoOthax8Z3We6Z uXvlNnckWf3t/sRWiLnDC657uM3OExsBdZ6aZjphtHJa+5hAntvszV+ft0QAygndhF dEYoxN4rkrI3qqD83nQqHcTaXsmN7s72sPYWMPsY= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id xACEOx2u115972 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 12 Nov 2019 08:24:59 -0600 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Tue, 12 Nov 2019 08:24:41 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Tue, 12 Nov 2019 08:24:42 -0600 Received: from uda0869644b.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id xACEOrBi036029; Tue, 12 Nov 2019 08:24:59 -0600 From: Benoit Parrot To: Tony Lindgren , Tero Kristo CC: , , , , , Benoit Parrot Subject: [Patch v3 03/10] ARM: OMAP: DRA7xx: Make CAM clock domain SWSUP only Date: Tue, 12 Nov 2019 08:27:46 -0600 Message-ID: <20191112142753.22976-4-bparrot@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191112142753.22976-1-bparrot@ti.com> References: <20191112142753.22976-1-bparrot@ti.com> MIME-Version: 1.0 Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Both CAL and VIP rely on this clock domain. But CAL DPHY require LVDSRX_96M_GFCLK to be active. When this domain is set to HWSUP the LVDSRX_96M_GFCLK is on;y active when VIP1 clock is also active. If only CAL on DRA72x (which uses the VIP2 clkctrl) probes the CAM domain is enabled but the LVDSRX_96M_GFCLK is left gated. Since LVDSRX_96M_GFCLK is sourcing the input clock to the DPHY then actual frame capture cannot start as the phy are inactive. So we either have to also enabled VIP1 even if we don't intend on using it or we need to set the CAM domain to use SWSUP only. This patch implements the latter. Signed-off-by: Benoit Parrot --- arch/arm/mach-omap2/clockdomains7xx_data.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-omap2/clockdomains7xx_data.c b/arch/arm/mach-omap2/clockdomains7xx_data.c index 3068802824b7..27835c4d1aa9 100644 --- a/arch/arm/mach-omap2/clockdomains7xx_data.c +++ b/arch/arm/mach-omap2/clockdomains7xx_data.c @@ -606,7 +606,7 @@ static struct clockdomain cam_7xx_clkdm = { .dep_bit = DRA7XX_CAM_STATDEP_SHIFT, .wkdep_srcs = cam_wkup_sleep_deps, .sleepdep_srcs = cam_wkup_sleep_deps, - .flags = CLKDM_CAN_HWSUP_SWSUP, + .flags = CLKDM_CAN_SWSUP, }; static struct clockdomain l4per_7xx_clkdm = { -- 2.17.1