Re: [PATCH 1/7] dt-bindings: clock: Add bindings for versal clock driver

[Rob Herring <robh@kernel.org>]

On Tue, Nov 12, 2019 at 02:51:46PM -0800, Stephen Boyd wrote:
> Quoting Rajan Vaja (2019-11-12 05:16:14)
> > diff --git a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml
> > new file mode 100644
> > index 0000000..da82f6a
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml
> > @@ -0,0 +1,67 @@
> > +# SPDX-License-Identifier: GPL-2.0
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/bindings/clock/xlnx,versal-clk.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Xilinx Versal clock controller
> > +
> > +maintainers:
> > +  - Michal Simek <michal.simek@xilinx.com>
> > +  - Jolly Shah <jolly.shah@xilinx.com>
> > +  - Rajan Vaja <rajan.vaja@xilinx.com>
> > +
> > +description: |
> > +  The clock controller is a h/w block of Xilinx versal clock tree. It reads
> 
> hardware instead of h/w
> 
> > +  required input clock frequencies from the devicetree and acts as clock
> > +  provider for all clock consumers of PS clocks. See clock_bindings.txt
> > +  for more information on the generic clock bindings.
> 
> Please drop this last sentence about clock_bindings.txt
> 
> > +
> > +properties:
> > +  compatible:
> > +    const: xlnx,versal-clk
> > +
> > +  "#clock-cells":
> > +    const: 1
> > +
> > +  clocks:
> > +    description: List of clock specifiers which are external input
> > +      clocks to the given clock controller.
> > +    minItems: 3
> > +    maxItems: 3

Can drop these. Implied by by 'items' list.

> > +    items:
> > +      - description: ref clk
> > +      - description: alternate ref clk
> > +      - description: pl alternate ref clk
> 
> What is "pl"? Can you clarify?
> 
> > +
> > +  clock-names:
> > +    minItems: 3
> > +    maxItems: 3

Same here.

> > +    items:
> > +      - const: ref_clk
> > +      - const: alt_ref_clk
> > +      - const: pl_alt_ref_clk

'_clk' is redundant.

> > +
> > +required:
> > +  - compatible
> > +  - "#clock-cells"
> > +  - clocks
> > +  - clock-names
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    firmware {
> > +      zynqmp_firmware: zynqmp-firmware {
> > +        compatible = "xlnx,zynqmp-firmware";
> > +        method = "smc";
> 
> Is there a way to say in the binding that this must be a child of a
> xlnx,zynqmp-firmware node? That would be ideal so we can constrain this
> to that location somehow.

Yes. Add the node name as a property to the f/w schema and reference 
($ref) this file and add 'select: false' to this one. The problem is the 
firmware binding is probably not yet a schema. Once it is a schema, this 
example will start failing because it's incomplete. For that reason, I 
prefer the examples in these cases (inc MFDs) in the base schema and not 
in the child node schemas.

> > +        versal_clk: clock-controller {
> > +          #clock-cells = <1>;
> > +          compatible = "xlnx,versal-clk";
> > +          clocks = <&ref_clk>, <&alt_ref_clk>, <&pl_alt_ref_clk>;
> > +          clock-names = "ref_clk", "alt_ref_clk", "pl_alt_ref_clk";
> > +        };
> > +      };
> > +    };
> > +...
>