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[46.91.226.206]) by smtp.gmail.com with ESMTPSA id q15sm25965385wrs.91.2019.11.18.22.34.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Nov 2019 22:34:28 -0800 (PST) Date: Tue, 19 Nov 2019 07:34:27 +0100 From: Thierry Reding To: Dmitry Osipenko Cc: Jonathan Hunter , Peter De Schrijver , Mikko Perttunen , Georgi Djakov , Rob Herring , linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: Re: [PATCH v1 14/29] memory: tegra: Add interconnect nodes for Terga20 display controllers Message-ID: <20191119063427.GG2462695@ulmo> References: <20191118200247.3567-1-digetx@gmail.com> <20191118200247.3567-15-digetx@gmail.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="I3tAPq1Rm2pUxvsp" Content-Disposition: inline In-Reply-To: <20191118200247.3567-15-digetx@gmail.com> User-Agent: Mutt/1.12.2 (2019-09-21) Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org --I3tAPq1Rm2pUxvsp Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, Nov 18, 2019 at 11:02:32PM +0300, Dmitry Osipenko wrote: > Add initial interconnect nodes that allow display controller driver > to perform memory bandwidth requests using interconnect API. >=20 > Signed-off-by: Dmitry Osipenko > --- > drivers/memory/tegra/tegra20.c | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) >=20 > diff --git a/drivers/memory/tegra/tegra20.c b/drivers/memory/tegra/tegra2= 0.c > index a8098bff91d9..dfcd9fdb7ce7 100644 > --- a/drivers/memory/tegra/tegra20.c > +++ b/drivers/memory/tegra/tegra20.c > @@ -3,6 +3,7 @@ > * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. > */ > =20 > +#include > #include > =20 > #include "mc.h" > @@ -280,6 +281,17 @@ static const struct tegra_mc_reset_ops tegra20_mc_re= set_ops =3D { > .reset_status =3D tegra20_mc_reset_status, > }; > =20 > +#define TEGRA20_MC_ICC(_name) \ > + { \ > + .name =3D #_name, \ > + .id =3D TEGRA_ICC_MC_##_name, \ > + } > + > +static const struct tegra_mc_icc_node tegra20_mc_icc_nodes[] =3D { > + TEGRA20_MC_ICC(DC), > + TEGRA20_MC_ICC(DCB), > +}; > + > const struct tegra_mc_soc tegra20_mc_soc =3D { > .clients =3D tegra20_mc_clients, > .num_clients =3D ARRAY_SIZE(tegra20_mc_clients), > @@ -290,4 +302,6 @@ const struct tegra_mc_soc tegra20_mc_soc =3D { > .reset_ops =3D &tegra20_mc_reset_ops, > .resets =3D tegra20_mc_resets, > .num_resets =3D ARRAY_SIZE(tegra20_mc_resets), > + .icc_nodes =3D tegra20_mc_icc_nodes, > + .num_icc_nodes =3D ARRAY_SIZE(tegra20_mc_icc_nodes), > }; As I mentioned, we already have most (if not all) of the information that we need for this in the various struct tegra_mc_client tables. Those tables also contain some definitions for latency allowance registers that we are eventually going to need to do more tweaking as you suggested in your cover letter. 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