RE: [EXT] Re: [v10 1/2] dt/bindings: clk: Add YAML schemas for LS1028A Display Clock bindings

Wen He
2019-12-04T01:36:30Z

> -----Original Message-----
> From: Michael Walle <michael@walle.cc>
> Sent: 2019年12月3日 5:32
> To: Rob Herring <robh@kernel.org>
> Cc: Wen He <wen.he_1@nxp.com>; Michael Turquette
> <mturquette@baylibre.com>; Stephen Boyd <sboyd@kernel.org>; Mark
> Rutland <mark.rutland@arm.com>; Leo Li <leoyang.li@nxp.com>;
> devicetree@vger.kernel.org; linux-clk@vger.kernel.org;
> linux-kernel@vger.kernel.org
> Subject: [EXT] Re: [v10 1/2] dt/bindings: clk: Add YAML schemas for LS1028A
> Display Clock bindings
>
> Caution: EXT Email
>
> Am 2019-12-02 19:47, schrieb Rob Herring:
> > On Wed, Nov 27, 2019 at 06:15:24PM +0800, Wen He wrote:
> >> LS1028A has a clock domain PXLCLK0 used for provide pixel clocks to
> >> Display output interface. Add a YAML schema for this.
> >>
> >> Signed-off-by: Wen He <wen.he_1@nxp.com>
> >> Signed-off-by: Michael Walle <michael@walle.cc>
> >> ---
> >> change in v10:
> >> - Add optional feild 'vco-frequency'.
> >>
> >> .../devicetree/bindings/clock/fsl,plldig.yaml | 54
> >> +++++++++++++++++++
> >> 1 file changed, 54 insertions(+)
> >> create mode 100644
> >> Documentation/devicetree/bindings/clock/fsl,plldig.yaml
> >>
> >> diff --git a/Documentation/devicetree/bindings/clock/fsl,plldig.yaml
> >> b/Documentation/devicetree/bindings/clock/fsl,plldig.yaml
> >> new file mode 100644
> >> index 000000000000..ee5b5c61a471
> >> --- /dev/null
> >> +++ b/Documentation/devicetree/bindings/clock/fsl,plldig.yaml
> >> @@ -0,0 +1,54 @@
> >> +# SPDX-License-Identifier: GPL-2.0
> >> +%YAML 1.2
> >> +---
> >> +$id:
> >> +https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdev
> >>
> +icetree.org%2Fschemas%2Fbindings%2Fclock%2Ffsl%2Cplldig.yaml%23&amp
> ;
> >>
> +data=02%7C01%7Cwen.he_1%40nxp.com%7Cc235afc88d844a2002ef08d77
> 76f1b33
> >>
> +%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C63710919139775
> 3988&amp
> >>
> +;sdata=VTmnjZ7tyLCmu21dymla8xUlpvWXMYA0A6FtcOg9u9U%3D&amp;res
> erved=0
> >> +$schema:
> >> +https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdev
> >>
> +icetree.org%2Fmeta-schemas%2Fcore.yaml%23&amp;data=02%7C01%7Cwe
> n.he_
> >>
> +1%40nxp.com%7Cc235afc88d844a2002ef08d7776f1b33%7C686ea1d3bc2b
> 4c6fa92
> >>
> +cd99c5c301635%7C0%7C0%7C637109191397753988&amp;sdata=CDVXbcg
> 9qikkXj6
> >> +bIATTtrBGWO%2FYUHo6ZYx5erqqRpM%3D&amp;reserved=0
> >> +
> >> +title: NXP QorIQ Layerscape LS1028A Display PIXEL Clock Binding
> >> +
> >> +maintainers:
> >> + - Wen He <wen.he_1@nxp.com>
> >> +
> >> +description: |
> >> + NXP LS1028A has a clock domain PXLCLK0 used for the Display output
> >> + interface in the display core, as implemented in TSMC CLN28HPM PLL.
> >> + which generate and offers pixel clocks to Display.
> >> +
> >> +properties:
> >> + compatible:
> >> + const: fsl,ls1028a-plldig
> >> +
> >> + reg:
> >> + maxItems: 1
> >> +
> >> + '#clock-cells':
> >> + const: 0
> >> +
> >> + vco-frequency:
> >
> > Needs vendor prefix and unit suffix:
> >
> > fsl,vco-hz
> >
> > Or you could perhaps just use 'clock-frequency'.
>
> Ok, fsl,vco-hz sounds good. clock-frequency sounds like it is the output.

Yes, fsl,vco-hz sounds good, I will update it in next version patch.

Thanks,
Wen
>
> -michael
>
> >> + $ref: '/schemas/types.yaml#/definitions/uint32'
> >> + description: Optional for VCO frequency of the PLL in Hertz.
> >> + The VCO frequency of this PLL cannot be changed during
> >> runtime
> >> + only at startup. Therefore, the output frequencies are very
> >> + limited and might not even closely match the requested
> >> frequency.
> >> + To work around this restriction the user may specify its own
> >> + desired VCO frequency for the PLL. The frequency has to be
> >> + in
> >> the
> >> + range of 650000000 to 1300000000.
> >> + If not set, the default frequency is 1188000000.
> >
> > A bunch of constraints you've listed here that should be schema rather
> > than freeform text:
> >
> > minimum: 650000000
> > maximum: 1300000000
> > default: 1188000000
> >
> >> +
> >> +required:
> >> + - compatible
> >> + - reg
> >> + - clocks
> >> + - '#clock-cells'
> >> +
> >> +examples:
> >> + # Display PIXEL Clock node:
> >> + - |
> >> + dpclk: clock-display@f1f0000 {
> >> + compatible = "fsl,ls1028a-plldig";
> >> + reg = <0x0 0xf1f0000 0x0 0xffff>;
> >> + #clock-cells = <0>;
> >> + clocks = <&osc_27m>;
> >> + };
> >> +
> >> +...
> >> --
> >> 2.17.1
> >>