From: Matthias Kaehlcke <mka@chromium.org>
To: Taniya Das <tdas@codeaurora.org>
Cc: agross@kernel.org, robh+dt@kernel.org,
bjorn.andersson@linaro.org, linux-arm-msm@vger.kernel.org,
devicetree@vger.kernel.org, Stephen Boyd <sboyd@kernel.org>,
Rajendra Nayak <rnayak@codeaurora.org>
Subject: Re: [PATCH v1] arm64: dts: sc7180: Add cpufreq HW node for cpu scaling
Date: Wed, 4 Dec 2019 16:46:03 -0800 [thread overview]
Message-ID: <20191205004603.GK228856@google.com> (raw)
In-Reply-To: <0101016ed02b6356-5165eaaa-6c54-47ff-a008-821c91831e56-000000@us-west-2.amazonses.com>
On Wed, Dec 04, 2019 at 09:08:54AM +0000, Taniya Das wrote:
> cpufreq hw node required to scale CPU frequency on sc7180.
>
> Signed-off-by: Taniya Das <tdas@codeaurora.org>
> ---
> arch/arm64/boot/dts/qcom/sc7180.dtsi | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> index c0ac0a1..7629995 100644
> --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> @@ -40,6 +40,7 @@
> reg = <0x0 0x0>;
> enable-method = "psci";
> next-level-cache = <&L2_0>;
> + qcom,freq-domain = <&cpufreq_hw 0>;
> L2_0: l2-cache {
> compatible = "cache";
> next-level-cache = <&L3_0>;
> @@ -55,6 +56,7 @@
> reg = <0x0 0x100>;
> enable-method = "psci";
> next-level-cache = <&L2_100>;
> + qcom,freq-domain = <&cpufreq_hw 0>;
> L2_100: l2-cache {
> compatible = "cache";
> next-level-cache = <&L3_0>;
> @@ -67,6 +69,7 @@
> reg = <0x0 0x200>;
> enable-method = "psci";
> next-level-cache = <&L2_200>;
> + qcom,freq-domain = <&cpufreq_hw 0>;
> L2_200: l2-cache {
> compatible = "cache";
> next-level-cache = <&L3_0>;
> @@ -79,6 +82,7 @@
> reg = <0x0 0x300>;
> enable-method = "psci";
> next-level-cache = <&L2_300>;
> + qcom,freq-domain = <&cpufreq_hw 0>;
> L2_300: l2-cache {
> compatible = "cache";
> next-level-cache = <&L3_0>;
> @@ -91,6 +95,7 @@
> reg = <0x0 0x400>;
> enable-method = "psci";
> next-level-cache = <&L2_400>;
> + qcom,freq-domain = <&cpufreq_hw 0>;
> L2_400: l2-cache {
> compatible = "cache";
> next-level-cache = <&L3_0>;
> @@ -103,6 +108,7 @@
> reg = <0x0 0x500>;
> enable-method = "psci";
> next-level-cache = <&L2_500>;
> + qcom,freq-domain = <&cpufreq_hw 0>;
> L2_500: l2-cache {
> compatible = "cache";
> next-level-cache = <&L3_0>;
> @@ -115,6 +121,7 @@
> reg = <0x0 0x600>;
> enable-method = "psci";
> next-level-cache = <&L2_600>;
> + qcom,freq-domain = <&cpufreq_hw 1>;
> L2_600: l2-cache {
> compatible = "cache";
> next-level-cache = <&L3_0>;
> @@ -127,6 +134,7 @@
> reg = <0x0 0x700>;
> enable-method = "psci";
> next-level-cache = <&L2_700>;
> + qcom,freq-domain = <&cpufreq_hw 1>;
> L2_700: l2-cache {
> compatible = "cache";
> next-level-cache = <&L3_0>;
> @@ -286,6 +294,17 @@
> status = "disabled";
> };
> };
> +
> + cpufreq_hw: cpufreq@18323000 {
> + compatible = "qcom,cpufreq-hw";
> + reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;
> + reg-names = "freq-domain0", "freq-domain1";
> +
> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
> + clock-names = "xo", "alternate";
> +
> + #freq-domain-cells = <1>;
> + };
> };
>
> timer {
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
prev parent reply other threads:[~2019-12-05 0:46 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-04 9:08 [PATCH v1] arm64: dts: sc7180: Add cpufreq HW node for cpu scaling Taniya Das
2019-12-05 0:46 ` Matthias Kaehlcke [this message]
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