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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id e7sm5610222pfe.168.2019.12.11.23.12.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2019 23:12:51 -0800 (PST) Date: Wed, 11 Dec 2019 23:12:48 -0800 From: Bjorn Andersson To: Brian Masney Cc: robdclark@gmail.com, sean@poorly.run, robh+dt@kernel.org, airlied@linux.ie, daniel@ffwll.ch, jcrouse@codeaurora.org, dianders@chromium.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org Subject: Re: [PATCH v2 2/4] drm/msm/gpu: add support for ocmem interconnect path Message-ID: <20191212071248.GK3143381@builder> References: <20191122012645.7430-1-masneyb@onstation.org> <20191122012645.7430-3-masneyb@onstation.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20191122012645.7430-3-masneyb@onstation.org> User-Agent: Mutt/1.12.2 (2019-09-21) Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Thu 21 Nov 17:26 PST 2019, Brian Masney wrote: > Some A3xx and all A4xx Adreno GPUs do not have GMEM inside the GPU core > and must use the On Chip MEMory (OCMEM) in order to be functional. > There's a separate interconnect path that needs to be setup to OCMEM. > Add support for this second path to the GPU core. > > In the downstream MSM 3.4 sources, the two interconnect paths for the > GPU are between: > > - MSM_BUS_MASTER_GRAPHICS_3D and MSM_BUS_SLAVE_EBI_CH0 > - MSM_BUS_MASTER_V_OCMEM_GFX3D and MSM_BUS_SLAVE_OCMEM > Reviewed-by: Bjorn Andersson > Signed-off-by: Brian Masney > --- > drivers/gpu/drm/msm/adreno/adreno_gpu.c | 14 +++++++++++++- > drivers/gpu/drm/msm/msm_gpu.h | 7 +++++++ > 2 files changed, 20 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c > index 0783e4b5486a..d27bdc999777 100644 > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c > @@ -887,10 +887,21 @@ static int adreno_get_pwrlevels(struct device *dev, > DBG("fast_rate=%u, slow_rate=27000000", gpu->fast_rate); > > /* Check for an interconnect path for the bus */ > - gpu->icc_path = of_icc_get(dev, NULL); > + gpu->icc_path = of_icc_get(dev, "gfx-mem"); > + if (!gpu->icc_path) { > + /* > + * Keep compatbility with device trees that don't have an > + * interconnect-names property. > + */ > + gpu->icc_path = of_icc_get(dev, NULL); > + } > if (IS_ERR(gpu->icc_path)) > gpu->icc_path = NULL; > > + gpu->ocmem_icc_path = of_icc_get(dev, "ocmem"); > + if (IS_ERR(gpu->ocmem_icc_path)) > + gpu->ocmem_icc_path = NULL; > + > return 0; > } > > @@ -977,6 +988,7 @@ void adreno_gpu_cleanup(struct adreno_gpu *adreno_gpu) > release_firmware(adreno_gpu->fw[i]); > > icc_put(gpu->icc_path); > + icc_put(gpu->ocmem_icc_path); > > msm_gpu_cleanup(&adreno_gpu->base); > } > diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h > index ab8f0f9c9dc8..be5bc2e8425c 100644 > --- a/drivers/gpu/drm/msm/msm_gpu.h > +++ b/drivers/gpu/drm/msm/msm_gpu.h > @@ -111,8 +111,15 @@ struct msm_gpu { > struct clk *ebi1_clk, *core_clk, *rbbmtimer_clk; > uint32_t fast_rate; > > + /* The gfx-mem interconnect path that's used by all GPU types. */ > struct icc_path *icc_path; > > + /* > + * Second interconnect path for some A3xx and all A4xx GPUs to the > + * On Chip MEMory (OCMEM). > + */ > + struct icc_path *ocmem_icc_path; > + > /* Hang and Inactivity Detection: > */ > #define DRM_MSM_INACTIVE_PERIOD 66 /* in ms (roughly four frames) */ > -- > 2.21.0 >