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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id bo9sm4620133pjb.21.2019.12.11.23.14.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2019 23:14:24 -0800 (PST) Date: Wed, 11 Dec 2019 23:14:22 -0800 From: Bjorn Andersson To: Brian Masney Cc: robdclark@gmail.com, sean@poorly.run, robh+dt@kernel.org, airlied@linux.ie, daniel@ffwll.ch, jcrouse@codeaurora.org, dianders@chromium.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org Subject: Re: [PATCH v2 1/4] dt-bindings: drm/msm/gpu: document second interconnect Message-ID: <20191212071422.GL3143381@builder> References: <20191122012645.7430-1-masneyb@onstation.org> <20191122012645.7430-2-masneyb@onstation.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20191122012645.7430-2-masneyb@onstation.org> User-Agent: Mutt/1.12.2 (2019-09-21) Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Thu 21 Nov 17:26 PST 2019, Brian Masney wrote: > Some A3xx and all A4xx Adreno GPUs do not have GMEM inside the GPU core > and must use the On Chip MEMory (OCMEM) in order to be functional. > There's a separate interconnect path that needs to be setup to OCMEM. > Let's document this second interconnect path that's available. Since > there's now two available interconnects, let's add the > interconnect-names property. > > Signed-off-by: Brian Masney Reviewed-by: Bjorn Andersson > --- > Documentation/devicetree/bindings/display/msm/gpu.txt | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/display/msm/gpu.txt b/Documentation/devicetree/bindings/display/msm/gpu.txt > index 2b8fd26c43b0..3e6cd3f64a78 100644 > --- a/Documentation/devicetree/bindings/display/msm/gpu.txt > +++ b/Documentation/devicetree/bindings/display/msm/gpu.txt > @@ -23,7 +23,10 @@ Required properties: > - iommus: optional phandle to an adreno iommu instance > - operating-points-v2: optional phandle to the OPP operating points > - interconnects: optional phandle to an interconnect provider. See > - ../interconnect/interconnect.txt for details. > + ../interconnect/interconnect.txt for details. Some A3xx and all A4xx platforms > + will have two paths; all others will have one path. > +- interconnect-names: The names of the interconnect paths that correspond to the > + interconnects property. Values must be gfx-mem and ocmem. > - qcom,gmu: For GMU attached devices a phandle to the GMU device that will > control the power for the GPU. Applicable targets: > - qcom,adreno-630.2 > @@ -76,6 +79,7 @@ Example a6xx (with GMU): > operating-points-v2 = <&gpu_opp_table>; > > interconnects = <&rsc_hlos MASTER_GFX3D &rsc_hlos SLAVE_EBI1>; > + interconnect-names = "gfx-mem"; > > qcom,gmu = <&gmu>; > > -- > 2.21.0 >