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[73.37.219.234]) by smtp.gmail.com with ESMTPSA id v38sm3984694ywh.63.2019.12.13.08.06.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Dec 2019 08:06:03 -0800 (PST) From: Adam Ford To: linux-arm-kernel@lists.infradead.org Cc: peng.fan@nxp.com, ping.bai@nxp.com, Adam Ford , Rob Herring , Mark Rutland , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH V2 6/7] ARM64: dts: imx8mm: Fix clocks and power domain for USB OTG Date: Fri, 13 Dec 2019 10:05:41 -0600 Message-Id: <20191213160542.15757-7-aford173@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191213160542.15757-1-aford173@gmail.com> References: <20191213160542.15757-1-aford173@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org There are two USB OTG controllers on the i.MX8M Mini, but currently neither are functional. According to the device tree entries published on the NXP kernel for the imx8m mini, these both need to be assigned to the proper clocks and power domain in order to function. This patch configures both USB OTG controllers to enable a missing clock and define the power domain so boards wishing to enable the USB OTG can do so. Signed-off-by: Adam Ford --- V2: No Change arch/arm64/boot/dts/freescale/imx8mm.dtsi | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index f38bed94bce2..dbeee4059c55 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -865,8 +865,11 @@ interrupts = ; clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>; clock-names = "usb1_ctrl_root_clk"; - assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; + assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>, + <&clk IMX8MM_CLK_USB_CORE_REF>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>, + <&clk IMX8MM_SYS_PLL1_100M>; + power-domains = <&pgc_otg1>; fsl,usbphy = <&usbphynop1>; fsl,usbmisc = <&usbmisc1 0>; status = "disabled"; @@ -884,8 +887,11 @@ interrupts = ; clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>; clock-names = "usb1_ctrl_root_clk"; - assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; + assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>, + <&clk IMX8MM_CLK_USB_CORE_REF>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>, + <&clk IMX8MM_SYS_PLL1_100M>; + power-domains = <&pgc_otg2>; fsl,usbphy = <&usbphynop2>; fsl,usbmisc = <&usbmisc2 0>; status = "disabled"; -- 2.20.1