* [PATCH] arm: dts: apq8084: Fix tsens kernel panic during boot and kernel warnings due to IRQ_TYPE_NONE interrupt type @ 2019-12-17 23:52 Victhor Foster 2019-12-18 6:28 ` Bjorn Andersson 0 siblings, 1 reply; 3+ messages in thread From: Victhor Foster @ 2019-12-17 23:52 UTC (permalink / raw) To: linux-arm-msm; +Cc: agross, robh+dt, mark.rutland, devicetree This patch fixes a kernel panic on the tsens driver that prevented APQ8084 platforms from booting, by adding a missing register property and the number of sensors, corrects all instances of IRQ_TYPE_NONE in interrupts, to avoid causing kernel warnings during boot, and also changes most interrupt properties to their respective macros, as defined by arm-gic.h. Signed-off by: Victhor Foster <victhor.foster@ufpe.br> --- arch/arm/boot/dts/qcom-apq8084.dtsi | 43 +++++++++++++++-------------- 1 file changed, 23 insertions(+), 20 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi index 0a0fb147ebb9..dc4ea3a8dc6d 100644 --- a/arch/arm/boot/dts/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /dts-v1/; +#include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/qcom,gcc-apq8084.h> #include <dt-bindings/gpio/gpio.h> @@ -184,7 +185,7 @@ cpu-pmu { compatible = "qcom,krait-pmu"; - interrupts = <1 7 0xf04>; + interrupts = <GIC_PPI 7 0xf04>; }; clocks { @@ -203,10 +204,10 @@ timer { compatible = "arm,armv7-timer"; - interrupts = <1 2 0xf08>, - <1 3 0xf08>, - <1 4 0xf08>, - <1 1 0xf08>; + interrupts = <GIC_PPI 2 0xf08>, + <GIC_PPI 3 0xf08>, + <GIC_PPI 4 0xf08>, + <GIC_PPI 1 0xf08>; clock-frequency = <19200000>; }; @@ -253,9 +254,11 @@ tsens: thermal-sensor@fc4a8000 { compatible = "qcom,msm8974-tsens"; - reg = <0xfc4a8000 0x2000>; + reg = <0xfc4a9000 0x1000>, /* TM */ + <0xfc4a8000 0x1000>; /* SROT */ nvmem-cells = <&tsens_calib>, <&tsens_backup>; nvmem-cell-names = "calib", "calib_backup"; + #qcom,sensors = <11>; #thermal-sensor-cells = <1>; }; @@ -269,50 +272,50 @@ frame@f9021000 { frame-number = <0>; - interrupts = <0 8 0x4>, - <0 7 0x4>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; reg = <0xf9021000 0x1000>, <0xf9022000 0x1000>; }; frame@f9023000 { frame-number = <1>; - interrupts = <0 9 0x4>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; reg = <0xf9023000 0x1000>; status = "disabled"; }; frame@f9024000 { frame-number = <2>; - interrupts = <0 10 0x4>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; reg = <0xf9024000 0x1000>; status = "disabled"; }; frame@f9025000 { frame-number = <3>; - interrupts = <0 11 0x4>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; reg = <0xf9025000 0x1000>; status = "disabled"; }; frame@f9026000 { frame-number = <4>; - interrupts = <0 12 0x4>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; reg = <0xf9026000 0x1000>; status = "disabled"; }; frame@f9027000 { frame-number = <5>; - interrupts = <0 13 0x4>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; reg = <0xf9027000 0x1000>; status = "disabled"; }; frame@f9028000 { frame-number = <6>; - interrupts = <0 14 0x4>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; reg = <0xf9028000 0x1000>; status = "disabled"; }; @@ -404,13 +407,13 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; - interrupts = <0 208 0>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; }; blsp2_uart2: serial@f995e000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0xf995e000 0x1000>; - interrupts = <0 114 0x0>; + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; clock-names = "core", "iface"; status = "disabled"; @@ -420,7 +423,7 @@ compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; reg-names = "hc_mem", "core_mem"; - interrupts = <0 123 0>, <0 138 0>; + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>, @@ -433,7 +436,7 @@ compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; reg-names = "hc_mem", "core_mem"; - interrupts = <0 125 0>, <0 221 0>; + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>, @@ -449,7 +452,7 @@ <0xfc4cb000 0x1000>, <0xfc4ca000 0x1000>; interrupt-names = "periph_irq"; - interrupts = <0 190 0>; + interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; qcom,ee = <0>; qcom,channel = <0>; #address-cells = <2>; @@ -463,7 +466,7 @@ compatible = "qcom,smd"; rpm { - interrupts = <0 168 1>; + interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; qcom,ipc = <&apcs 8 0>; qcom,smd-edge = <15>; -- 2.24.0 ^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] arm: dts: apq8084: Fix tsens kernel panic during boot and kernel warnings due to IRQ_TYPE_NONE interrupt type 2019-12-17 23:52 [PATCH] arm: dts: apq8084: Fix tsens kernel panic during boot and kernel warnings due to IRQ_TYPE_NONE interrupt type Victhor Foster @ 2019-12-18 6:28 ` Bjorn Andersson 2019-12-19 2:58 ` Victhor Foster 0 siblings, 1 reply; 3+ messages in thread From: Bjorn Andersson @ 2019-12-18 6:28 UTC (permalink / raw) To: Victhor Foster; +Cc: linux-arm-msm, agross, robh+dt, mark.rutland, devicetree On Tue 17 Dec 15:52 PST 2019, Victhor Foster wrote: > This patch fixes a kernel panic on the tsens driver that prevented APQ8084 platforms from booting, by adding a missing register property and the number of sensors I was under the impression that the tsens driver did maintain backwards compatibility wrt a single reg cell... > , corrects all instances of IRQ_TYPE_NONE in interrupts, to avoid causing kernel warnings during boot, and also changes most interrupt properties to their respective macros, as defined by arm-gic.h. > > Signed-off by: Victhor Foster <victhor.foster@ufpe.br> The content looks good, but can you please split it in two; one for the tsens change and one for the interrupts cells? And please limit your commit message to 72 chars. Thanks, Bjorn > --- > arch/arm/boot/dts/qcom-apq8084.dtsi | 43 +++++++++++++++-------------- > 1 file changed, 23 insertions(+), 20 deletions(-) > > diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi > index 0a0fb147ebb9..dc4ea3a8dc6d 100644 > --- a/arch/arm/boot/dts/qcom-apq8084.dtsi > +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi > @@ -1,6 +1,7 @@ > // SPDX-License-Identifier: GPL-2.0 > /dts-v1/; > > +#include <dt-bindings/interrupt-controller/arm-gic.h> > #include <dt-bindings/clock/qcom,gcc-apq8084.h> > #include <dt-bindings/gpio/gpio.h> > > @@ -184,7 +185,7 @@ > > cpu-pmu { > compatible = "qcom,krait-pmu"; > - interrupts = <1 7 0xf04>; > + interrupts = <GIC_PPI 7 0xf04>; > }; > > clocks { > @@ -203,10 +204,10 @@ > > timer { > compatible = "arm,armv7-timer"; > - interrupts = <1 2 0xf08>, > - <1 3 0xf08>, > - <1 4 0xf08>, > - <1 1 0xf08>; > + interrupts = <GIC_PPI 2 0xf08>, > + <GIC_PPI 3 0xf08>, > + <GIC_PPI 4 0xf08>, > + <GIC_PPI 1 0xf08>; > clock-frequency = <19200000>; > }; > > @@ -253,9 +254,11 @@ > > tsens: thermal-sensor@fc4a8000 { > compatible = "qcom,msm8974-tsens"; > - reg = <0xfc4a8000 0x2000>; > + reg = <0xfc4a9000 0x1000>, /* TM */ > + <0xfc4a8000 0x1000>; /* SROT */ > nvmem-cells = <&tsens_calib>, <&tsens_backup>; > nvmem-cell-names = "calib", "calib_backup"; > + #qcom,sensors = <11>; > #thermal-sensor-cells = <1>; > }; > > @@ -269,50 +272,50 @@ > > frame@f9021000 { > frame-number = <0>; > - interrupts = <0 8 0x4>, > - <0 7 0x4>; > + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; > reg = <0xf9021000 0x1000>, > <0xf9022000 0x1000>; > }; > > frame@f9023000 { > frame-number = <1>; > - interrupts = <0 9 0x4>; > + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; > reg = <0xf9023000 0x1000>; > status = "disabled"; > }; > > frame@f9024000 { > frame-number = <2>; > - interrupts = <0 10 0x4>; > + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; > reg = <0xf9024000 0x1000>; > status = "disabled"; > }; > > frame@f9025000 { > frame-number = <3>; > - interrupts = <0 11 0x4>; > + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; > reg = <0xf9025000 0x1000>; > status = "disabled"; > }; > > frame@f9026000 { > frame-number = <4>; > - interrupts = <0 12 0x4>; > + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; > reg = <0xf9026000 0x1000>; > status = "disabled"; > }; > > frame@f9027000 { > frame-number = <5>; > - interrupts = <0 13 0x4>; > + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; > reg = <0xf9027000 0x1000>; > status = "disabled"; > }; > > frame@f9028000 { > frame-number = <6>; > - interrupts = <0 14 0x4>; > + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; > reg = <0xf9028000 0x1000>; > status = "disabled"; > }; > @@ -404,13 +407,13 @@ > #gpio-cells = <2>; > interrupt-controller; > #interrupt-cells = <2>; > - interrupts = <0 208 0>; > + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; > }; > > blsp2_uart2: serial@f995e000 { > compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; > reg = <0xf995e000 0x1000>; > - interrupts = <0 114 0x0>; > + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; > clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; > clock-names = "core", "iface"; > status = "disabled"; > @@ -420,7 +423,7 @@ > compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"; > reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; > reg-names = "hc_mem", "core_mem"; > - interrupts = <0 123 0>, <0 138 0>; > + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; > interrupt-names = "hc_irq", "pwr_irq"; > clocks = <&gcc GCC_SDCC1_APPS_CLK>, > <&gcc GCC_SDCC1_AHB_CLK>, > @@ -433,7 +436,7 @@ > compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"; > reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; > reg-names = "hc_mem", "core_mem"; > - interrupts = <0 125 0>, <0 221 0>; > + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; > interrupt-names = "hc_irq", "pwr_irq"; > clocks = <&gcc GCC_SDCC2_APPS_CLK>, > <&gcc GCC_SDCC2_AHB_CLK>, > @@ -449,7 +452,7 @@ > <0xfc4cb000 0x1000>, > <0xfc4ca000 0x1000>; > interrupt-names = "periph_irq"; > - interrupts = <0 190 0>; > + interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; > qcom,ee = <0>; > qcom,channel = <0>; > #address-cells = <2>; > @@ -463,7 +466,7 @@ > compatible = "qcom,smd"; > > rpm { > - interrupts = <0 168 1>; > + interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; > qcom,ipc = <&apcs 8 0>; > qcom,smd-edge = <15>; > > -- > 2.24.0 ^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] arm: dts: apq8084: Fix tsens kernel panic during boot and kernel warnings due to IRQ_TYPE_NONE interrupt type 2019-12-18 6:28 ` Bjorn Andersson @ 2019-12-19 2:58 ` Victhor Foster 0 siblings, 0 replies; 3+ messages in thread From: Victhor Foster @ 2019-12-19 2:58 UTC (permalink / raw) To: linux-arm-msm; +Cc: agross, robh+dt, mark rutland, devicetree ----- On Dec 18, 2019, at 3:28 AM, Bjorn Andersson bjorn.andersson@linaro.org wrote: > On Tue 17 Dec 15:52 PST 2019, Victhor Foster wrote: > >> This patch fixes a kernel panic on the tsens driver that prevented APQ8084 >> platforms from booting, by adding a missing register property and the number of >> sensors > > I was under the impression that the tsens driver did maintain backwards > compatibility wrt a single reg cell... > I wrote this patch based on 5.5-rc1, which was the latest version in the linux-stable repository at the time. I did notice that patch on the mailing list, but I hadn't tested it. The peripheral is compatible with the new driver, from what I can tell, so I thought this change made sense. >> , corrects all instances of IRQ_TYPE_NONE in interrupts, to avoid causing kernel >> warnings during boot, and also changes most interrupt properties to their >> respective macros, as defined by arm-gic.h. >> >> Signed-off by: Victhor Foster <victhor.foster@ufpe.br> > > The content looks good, but can you please split it in two; one for the > tsens change and one for the interrupts cells? And please limit your > commit message to 72 chars. > Sure, I'll do the changes as requested and submit the patch again, I'll keep the character limit in mind. Thanks for the feedback. > Thanks, > Bjorn > Thank you, Victhor >> --- >> arch/arm/boot/dts/qcom-apq8084.dtsi | 43 +++++++++++++++-------------- >> 1 file changed, 23 insertions(+), 20 deletions(-) >> >> diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi >> b/arch/arm/boot/dts/qcom-apq8084.dtsi >> index 0a0fb147ebb9..dc4ea3a8dc6d 100644 >> --- a/arch/arm/boot/dts/qcom-apq8084.dtsi >> +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi >> @@ -1,6 +1,7 @@ >> // SPDX-License-Identifier: GPL-2.0 >> /dts-v1/; >> >> +#include <dt-bindings/interrupt-controller/arm-gic.h> >> #include <dt-bindings/clock/qcom,gcc-apq8084.h> >> #include <dt-bindings/gpio/gpio.h> >> >> @@ -184,7 +185,7 @@ >> >> cpu-pmu { >> compatible = "qcom,krait-pmu"; >> - interrupts = <1 7 0xf04>; >> + interrupts = <GIC_PPI 7 0xf04>; >> }; >> >> clocks { >> @@ -203,10 +204,10 @@ >> >> timer { >> compatible = "arm,armv7-timer"; >> - interrupts = <1 2 0xf08>, >> - <1 3 0xf08>, >> - <1 4 0xf08>, >> - <1 1 0xf08>; >> + interrupts = <GIC_PPI 2 0xf08>, >> + <GIC_PPI 3 0xf08>, >> + <GIC_PPI 4 0xf08>, >> + <GIC_PPI 1 0xf08>; >> clock-frequency = <19200000>; >> }; >> >> @@ -253,9 +254,11 @@ >> >> tsens: thermal-sensor@fc4a8000 { >> compatible = "qcom,msm8974-tsens"; >> - reg = <0xfc4a8000 0x2000>; >> + reg = <0xfc4a9000 0x1000>, /* TM */ >> + <0xfc4a8000 0x1000>; /* SROT */ >> nvmem-cells = <&tsens_calib>, <&tsens_backup>; >> nvmem-cell-names = "calib", "calib_backup"; >> + #qcom,sensors = <11>; >> #thermal-sensor-cells = <1>; >> }; >> >> @@ -269,50 +272,50 @@ >> >> frame@f9021000 { >> frame-number = <0>; >> - interrupts = <0 8 0x4>, >> - <0 7 0x4>; >> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; >> reg = <0xf9021000 0x1000>, >> <0xf9022000 0x1000>; >> }; >> >> frame@f9023000 { >> frame-number = <1>; >> - interrupts = <0 9 0x4>; >> + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; >> reg = <0xf9023000 0x1000>; >> status = "disabled"; >> }; >> >> frame@f9024000 { >> frame-number = <2>; >> - interrupts = <0 10 0x4>; >> + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; >> reg = <0xf9024000 0x1000>; >> status = "disabled"; >> }; >> >> frame@f9025000 { >> frame-number = <3>; >> - interrupts = <0 11 0x4>; >> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; >> reg = <0xf9025000 0x1000>; >> status = "disabled"; >> }; >> >> frame@f9026000 { >> frame-number = <4>; >> - interrupts = <0 12 0x4>; >> + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; >> reg = <0xf9026000 0x1000>; >> status = "disabled"; >> }; >> >> frame@f9027000 { >> frame-number = <5>; >> - interrupts = <0 13 0x4>; >> + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; >> reg = <0xf9027000 0x1000>; >> status = "disabled"; >> }; >> >> frame@f9028000 { >> frame-number = <6>; >> - interrupts = <0 14 0x4>; >> + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; >> reg = <0xf9028000 0x1000>; >> status = "disabled"; >> }; >> @@ -404,13 +407,13 @@ >> #gpio-cells = <2>; >> interrupt-controller; >> #interrupt-cells = <2>; >> - interrupts = <0 208 0>; >> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; >> }; >> >> blsp2_uart2: serial@f995e000 { >> compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; >> reg = <0xf995e000 0x1000>; >> - interrupts = <0 114 0x0>; >> + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; >> clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; >> clock-names = "core", "iface"; >> status = "disabled"; >> @@ -420,7 +423,7 @@ >> compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"; >> reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; >> reg-names = "hc_mem", "core_mem"; >> - interrupts = <0 123 0>, <0 138 0>; >> + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 >> IRQ_TYPE_LEVEL_HIGH>; >> interrupt-names = "hc_irq", "pwr_irq"; >> clocks = <&gcc GCC_SDCC1_APPS_CLK>, >> <&gcc GCC_SDCC1_AHB_CLK>, >> @@ -433,7 +436,7 @@ >> compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"; >> reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; >> reg-names = "hc_mem", "core_mem"; >> - interrupts = <0 125 0>, <0 221 0>; >> + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 221 >> IRQ_TYPE_LEVEL_HIGH>; >> interrupt-names = "hc_irq", "pwr_irq"; >> clocks = <&gcc GCC_SDCC2_APPS_CLK>, >> <&gcc GCC_SDCC2_AHB_CLK>, >> @@ -449,7 +452,7 @@ >> <0xfc4cb000 0x1000>, >> <0xfc4ca000 0x1000>; >> interrupt-names = "periph_irq"; >> - interrupts = <0 190 0>; >> + interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; >> qcom,ee = <0>; >> qcom,channel = <0>; >> #address-cells = <2>; >> @@ -463,7 +466,7 @@ >> compatible = "qcom,smd"; >> >> rpm { >> - interrupts = <0 168 1>; >> + interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; >> qcom,ipc = <&apcs 8 0>; >> qcom,smd-edge = <15>; >> >> -- > > 2.24.0 ^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2019-12-19 2:58 UTC | newest] Thread overview: 3+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2019-12-17 23:52 [PATCH] arm: dts: apq8084: Fix tsens kernel panic during boot and kernel warnings due to IRQ_TYPE_NONE interrupt type Victhor Foster 2019-12-18 6:28 ` Bjorn Andersson 2019-12-19 2:58 ` Victhor Foster
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