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[46.91.239.63]) by smtp.gmail.com with ESMTPSA id f16sm17271848wrm.65.2019.12.22.06.10.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 22 Dec 2019 06:10:56 -0800 (PST) From: Thierry Reding To: Thierry Reding Cc: Rob Herring , Jon Hunter , linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 12/13] arm64: tegra: Add external memory controller on Tegra186 Date: Sun, 22 Dec 2019 15:10:34 +0100 Message-Id: <20191222141035.1649937-13-thierry.reding@gmail.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20191222141035.1649937-1-thierry.reding@gmail.com> References: <20191222141035.1649937-1-thierry.reding@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Thierry Reding Add the external memory controller as a child device of the memory controller on Tegra186. The memory controller really represents the memory subsystem that encompasses both the memory and external memory controllers. The external memory controller uses the BPMP to obtain the list of supported EMC frequencies and set the EMC frequency. Also set up the dma-ranges property to describe that all memory clients can address up to 40 bits using the memory controller client interface (MCCIF), unless otherwise limited by the DMA engines of the hardware. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 584498a999d4..dba7f57469c5 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -144,6 +144,27 @@ memory-controller@2c00000 { reg = <0x0 0x02c00000 0x0 0xb0000>; interrupts = ; status = "disabled"; + + #address-cells = <2>; + #size-cells = <2>; + + ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>; + + /* + * Memory clients have access to all 40 bits that the memory + * controller can address. + */ + dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; + + emc: external-memory-controller@2c60000 { + compatible = "nvidia,tegra186-emc"; + reg = <0x0 0x02c60000 0x0 0x50000>; + interrupts = ; + clocks = <&bpmp TEGRA186_CLK_EMC>; + clock-names = "emc"; + + nvidia,bpmp = <&bpmp>; + }; }; timer@3010000 { -- 2.24.1