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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id i9sm45974852pfk.24.2019.12.28.22.33.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 28 Dec 2019 22:33:27 -0800 (PST) Date: Sat, 28 Dec 2019 22:33:25 -0800 From: Bjorn Andersson To: Sharat Masetty Cc: freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, dri-devel@freedesktop.org, linux-arm-msm@vger.kernel.org Subject: Re: [PATCH] arm: dts: sc7180: Add A618 gpu dt blob Message-ID: <20191229063325.GP3755841@builder> References: <0101016ecc56c5c5-ab66c0ce-da45-4d8e-9cac-8f6be69001d3-000000@us-west-2.amazonses.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <0101016ecc56c5c5-ab66c0ce-da45-4d8e-9cac-8f6be69001d3-000000@us-west-2.amazonses.com> User-Agent: Mutt/1.12.2 (2019-09-21) Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Tue 03 Dec 07:17 PST 2019, Sharat Masetty wrote: Please update subject to "arm64: dts: qcom: sc7180: Add A618 GPU nodes" > This patch adds the required dt nodes and properties > to enabled A618 GPU. > > Signed-off-by: Sharat Masetty > --- > arch/arm64/boot/dts/qcom/sc7180.dtsi | 116 +++++++++++++++++++++++++++++++++++ > 1 file changed, 116 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi > index c3db2e5..31223d0 100644 > --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi > @@ -18,6 +18,8 @@ > #include > #include > #include > +#include > +#include Please maintain sort order of includes. > > / { > interrupt-parent = <&intc>; > @@ -733,6 +735,120 @@ > #power-domain-cells = <1>; > }; > > + gpu: gpu@5000000 { Please rebase this on linux-next and ensure to maintain the sort order. > + compatible = "qcom,adreno-618.0", "qcom,adreno"; > + #stream-id-cells = <16>; > + reg = <0 0x5000000 0 0x40000>, <0 0x509e000 0 0x1000>, Please pad addresses to 8 digits. > + <0 0x5061000 0 0x800>; > + reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc"; > + > + interrupts = ; > + > + iommus = <&adreno_smmu 0>; > + > + operating-points-v2 = <&gpu_opp_table>; > + > + interconnects = <&gem_noc 35 &mc_virt 512>; Please use the defines for these ports. > + > + qcom,gmu = <&gmu>; You can reduce the number of empty lines above. > + > + gpu_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-800000000 { > + opp-hz = /bits/ 64 <800000000>; > + opp-level = ; > + }; > + > + opp-650000000 { > + opp-hz = /bits/ 64 <650000000>; > + opp-level = ; > + }; > + > + opp-565000000 { > + opp-hz = /bits/ 64 <565000000>; > + opp-level = ; > + }; > + > + opp-430000000 { > + opp-hz = /bits/ 64 <430000000>; > + opp-level = ; > + }; > + > + opp-355000000 { The indentation is off here. > + opp-hz = /bits/ 64 <355000000>; > + opp-level = ; > + }; > + > + opp-267000000 { And here. > + opp-hz = /bits/ 64 <267000000>; > + opp-level = ; > + }; > + > + opp-180000000 { > + opp-hz = /bits/ 64 <180000000>; > + opp-level = ; > + }; > + }; > + }; > + > + adreno_smmu: iommu@5040000 { > + compatible = "qcom,sc7180-smmu-v2", "qcom,smmu-v2"; > + reg = <0 0x5040000 0 0x10000>; > + #iommu-cells = <1>; > + #global-interrupts = <2>; > + interrupts = , > + , > + , > + , > + , > + , > + , > + , > + , > + ; > + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, > + <&gcc GCC_GPU_CFG_AHB_CLK>, > + <&gcc GCC_DDRSS_GPU_AXI_CLK>; > + > + clock-names = "bus", "iface", "mem_iface_clk"; > + power-domains = <&gpucc CX_GDSC>; > + }; > + > + gmu: gmu@506a000 { > + compatible="qcom,adreno-gmu-618", "qcom,adreno-gmu"; > + > + reg = <0 0x506a000 0 0x31000>, Extra spaces after = > + <0 0xb290000 0 0x10000>, > + <0 0xb490000 0 0x10000>; > + reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; > + > + interrupts = , > + ; > + interrupt-names = "hfi", "gmu"; > + > + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, > + <&gpucc GPU_CC_CXO_CLK>, > + <&gcc GCC_DDRSS_GPU_AXI_CLK>, > + <&gcc GCC_GPU_MEMNOC_GFX_CLK>; > + clock-names = "gmu", "cxo", "axi", "memnoc"; > + > + power-domains = <&gpucc CX_GDSC>; > + > + iommus = <&adreno_smmu 5>; > + > + operating-points-v2 = <&gmu_opp_table>; As above, please drop a few of these empty lines. Regards, Bjorn > + > + gmu_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-200000000 { > + opp-hz = /bits/ 64 <200000000>; > + opp-level = ; > + }; > + }; > + }; > + > apps_smmu: iommu@15000000 { > compatible = "qcom,sc7180-smmu-500", "arm,mmu-500"; > reg = <0 0x15000000 0 0x100000>; > -- > 1.9.1 >