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Sat, 07 Jun 2025 04:43:47 -0700 (PDT) Message-ID: <201c7188-eaf7-4492-84a6-66d839062d8d@tuxon.dev> Date: Sat, 7 Jun 2025 14:43:45 +0300 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 8/9] ARM: dts: microchip: sama7d65: Add CAN bus support To: Ryan.Wanner@microchip.com, herbert@gondor.apana.org.au, davem@davemloft.net, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, nicolas.ferre@microchip.com, alexandre.belloni@bootlin.com, olivia@selenic.com Cc: linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <445c4c72243f1ba85e3681ba026cfefaf6036890.1747077616.git.Ryan.Wanner@microchip.com> From: Claudiu Beznea Content-Language: en-US In-Reply-To: <445c4c72243f1ba85e3681ba026cfefaf6036890.1747077616.git.Ryan.Wanner@microchip.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 12.05.2025 22:27, Ryan.Wanner@microchip.com wrote: > From: Ryan Wanner > > Add support for CAN bus to the SAMA7D65 SoC. > > Signed-off-by: Ryan Wanner Reviewed-by: Claudiu Beznea > --- > arch/arm/boot/dts/microchip/sama7d65.dtsi | 80 +++++++++++++++++++++++ > 1 file changed, 80 insertions(+) > > diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi > index 796909fa2368..a62d2ef9fcab 100644 > --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi > +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi > @@ -163,6 +163,86 @@ chipid@e0020000 { > reg = <0xe0020000 0x8>; > }; > > + can0: can@e0828000 { > + compatible = "bosch,m_can"; > + reg = <0xe0828000 0x200>, <0x100000 0x7800>; > + reg-names = "m_can", "message_ram"; > + interrupts = , > + ; > + interrupt-names = "int0", "int1"; > + clocks = <&pmc PMC_TYPE_PERIPHERAL 58>, <&pmc PMC_TYPE_GCK 58>; > + clock-names = "hclk", "cclk"; > + assigned-clocks = <&pmc PMC_TYPE_GCK 58>; > + assigned-clock-rates = <40000000>; > + assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; > + bosch,mram-cfg = <0x3400 0 0 64 0 0 32 32>; > + status = "disabled"; > + }; > + > + can1: can@e082c000 { > + compatible = "bosch,m_can"; > + reg = <0xe082c000 0x200>, <0x100000 0xbc00>; > + reg-names = "m_can", "message_ram"; > + interrupts = , > + ; > + interrupt-names = "int0", "int1"; > + clocks = <&pmc PMC_TYPE_PERIPHERAL 59>, <&pmc PMC_TYPE_GCK 59>; > + clock-names = "hclk", "cclk"; > + assigned-clocks = <&pmc PMC_TYPE_GCK 59>; > + assigned-clock-rates = <40000000>; > + assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; > + bosch,mram-cfg = <0x7800 0 0 64 0 0 32 32>; > + status = "disabled"; > + }; > + > + can2: can@e0830000 { > + compatible = "bosch,m_can"; > + reg = <0xe0830000 0x200>, <0x100000 0x10000>; > + reg-names = "m_can", "message_ram"; > + interrupts = , > + ; > + interrupt-names = "int0", "int1"; > + clocks = <&pmc PMC_TYPE_PERIPHERAL 60>, <&pmc PMC_TYPE_GCK 60>; > + clock-names = "hclk", "cclk"; > + assigned-clocks = <&pmc PMC_TYPE_GCK 60>; > + assigned-clock-rates = <40000000>; > + assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; > + bosch,mram-cfg = <0xbc00 0 0 64 0 0 32 32>; > + status = "disabled"; > + }; > + > + can3: can@e0834000 { > + compatible = "bosch,m_can"; > + reg = <0xe0834000 0x200>, <0x110000 0x4400>; > + reg-names = "m_can", "message_ram"; > + interrupts = , > + ; > + interrupt-names = "int0", "int1"; > + clocks = <&pmc PMC_TYPE_PERIPHERAL 61>, <&pmc PMC_TYPE_GCK 61>; > + clock-names = "hclk", "cclk"; > + assigned-clocks = <&pmc PMC_TYPE_GCK 61>; > + assigned-clock-rates = <40000000>; > + assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; > + bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>; > + status = "disabled"; > + }; > + > + can4: can@e0838000 { > + compatible = "bosch,m_can"; > + reg = <0xe0838000 0x200>, <0x110000 0x8800>; > + reg-names = "m_can", "message_ram"; > + interrupts = , > + ; > + interrupt-names = "int0", "int1"; > + clocks = <&pmc PMC_TYPE_PERIPHERAL 62>, <&pmc PMC_TYPE_GCK 62>; > + clock-names = "hclk", "cclk"; > + assigned-clocks = <&pmc PMC_TYPE_GCK 62>; > + assigned-clock-rates = <40000000>; > + assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; > + bosch,mram-cfg = <0x4400 0 0 64 0 0 32 32>; > + status = "disabled"; > + }; > + > dma2: dma-controller@e1200000 { > compatible = "microchip,sama7d65-dma", "microchip,sama7g5-dma"; > reg = <0xe1200000 0x1000>;