From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BF452C2D0D1 for ; Mon, 6 Jan 2020 10:19:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 957A620848 for ; Mon, 6 Jan 2020 10:19:35 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="WLiZYr1l" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726789AbgAFKTe (ORCPT ); Mon, 6 Jan 2020 05:19:34 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:55842 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726313AbgAFKTc (ORCPT ); Mon, 6 Jan 2020 05:19:32 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 006AJMaX017749; Mon, 6 Jan 2020 04:19:22 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1578305962; bh=z6P5mMgqQceKk5MBZ5w8ZWdHXIS1bakzmTv6Tp6ayC4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=WLiZYr1lncnTbPM7XyKEx5MUsW1DBS9AAcavwUECIE6DZUAkwu8nLC2gZf1jShkTQ NrTKxuZuJBSBu6kuGLh4uTlwWRtnsRU0bw6Gd0rRu1SAFpD0Mkpqx/4yal+7gsV+bE ZzIDzT2vDgUB27zgWT7VjFBWVEl6cemA5ojapDwk= Received: from DLEE106.ent.ti.com (dlee106.ent.ti.com [157.170.170.36]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 006AJMq0039619 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 6 Jan 2020 04:19:22 -0600 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Mon, 6 Jan 2020 04:19:21 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Mon, 6 Jan 2020 04:19:21 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 006AIqXx118652; Mon, 6 Jan 2020 04:19:17 -0600 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , Arnd Bergmann , Andrew Murray CC: , , , Subject: [PATCH v2 07/14] PCI: cadence: Allow pci_host_bridge to have custom pci_ops Date: Mon, 6 Jan 2020 15:50:51 +0530 Message-ID: <20200106102058.19183-8-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200106102058.19183-1-kishon@ti.com> References: <20200106102058.19183-1-kishon@ti.com> MIME-Version: 1.0 Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Certain platforms like TI's J721E allows only 32-bit configuration space access. In such cases pci_generic_config_read and pci_generic_config_write cannot be used. Add support in Cadence core to let pci_host_bridge have custom pci_ops. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/cadence/pcie-cadence-host.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c index d6a38b74371c..29d3afd8cf06 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-host.c +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c @@ -288,7 +288,8 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) list_splice_init(&resources, &bridge->windows); bridge->dev.parent = dev; bridge->busnr = pcie->bus; - bridge->ops = &cdns_pcie_host_ops; + if (!bridge->ops) + bridge->ops = &cdns_pcie_host_ops; bridge->map_irq = of_irq_parse_and_map_pci; bridge->swizzle_irq = pci_common_swizzle; -- 2.17.1