From: Shawn Guo <shawn.guo@linaro.org>
To: Wei Xu <xuwei5@hisilicon.com>
Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
Shawn Guo <shawn.guo@linaro.org>
Subject: [PATCH] arm64: dts: hi3798cv200: correct PCIe 'bus-range' setting
Date: Tue, 7 Jan 2020 20:29:08 +0800 [thread overview]
Message-ID: <20200107122908.18025-1-shawn.guo@linaro.org> (raw)
The PCIe 'bus-range' setting is incorrect and causing the following
message during boot.
pci_bus 0000:01: busn_res: can not insert [bus 01-ff] under [bus 00-0f] (conflicts with (null) [bus 00-0f])
Correct it to get rid of the message.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
---
arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
index 0a30aaae6bf2..4d1a3d1fc31c 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
@@ -569,7 +569,7 @@
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
- bus-range = <0 15>;
+ bus-range = <0x00 0xff>;
num-lanes = <1>;
ranges = <0x81000000 0x0 0x00000000 0x4f00000 0x0 0x100000
0x82000000 0x0 0x3000000 0x3000000 0x0 0x01f00000>;
--
2.17.1
next reply other threads:[~2020-01-07 12:29 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-07 12:29 Shawn Guo [this message]
2020-01-08 11:37 ` [PATCH] arm64: dts: hi3798cv200: correct PCIe 'bus-range' setting Wei Xu
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