From: Rob Herring <robh@kernel.org>
To: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Arnd Bergmann <arnd@arndb.de>,
Andrew Murray <andrew.murray@arm.com>,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2 01/14] dt-bindings: PCI: cadence: Add PCIe RC/EP DT schema for Cadence PCIe
Date: Tue, 7 Jan 2020 21:43:14 -0600 [thread overview]
Message-ID: <20200108034314.GA5412@bogus> (raw)
In-Reply-To: <20200106102058.19183-2-kishon@ti.com>
On Mon, Jan 06, 2020 at 03:50:45PM +0530, Kishon Vijay Abraham I wrote:
> Add PCIe Host (RC) and Endpoint (EP) device tree schema for Cadence
> PCIe core library. Platforms using Cadence PCIe core can include the
> schemas added here in the platform specific schemas.
>
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
> .../devicetree/bindings/pci/cdns-pcie-ep.yaml | 20 ++++++++++++
> .../bindings/pci/cdns-pcie-host.yaml | 30 +++++++++++++++++
> .../devicetree/bindings/pci/cdns-pcie.yaml | 32 +++++++++++++++++++
> 3 files changed, 82 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pci/cdns-pcie-ep.yaml
> create mode 100644 Documentation/devicetree/bindings/pci/cdns-pcie-host.yaml
> create mode 100644 Documentation/devicetree/bindings/pci/cdns-pcie.yaml
Need to remove the old files.
Note that I posted a conversion of Cadence host[1]. Yours goes further,
but please compare and add anything mine has that yours doesn't.
[1] https://lore.kernel.org/linux-pci/20191231193903.15929-2-robh@kernel.org/
>
> diff --git a/Documentation/devicetree/bindings/pci/cdns-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/cdns-pcie-ep.yaml
> new file mode 100644
> index 000000000000..36aaae5931c3
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/cdns-pcie-ep.yaml
> @@ -0,0 +1,20 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
> +%YAML 1.2
> +--
> +$id: "http://devicetree.org/schemas/pci/cdns-pcie-ep.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Cadence PCIe Endpoint
> +
> +maintainers:
> + - Tom Joseph <tjoseph@cadence.com>
> +
> +allOf:
> + - $ref: "cdns-pcie.yaml#"
> +
> +properties:
> + max-functions:
> + description: Maximum number of functions that can be configured (default 1)
> + allOf:
> + - $ref: /schemas/types.yaml#/definitions/uint8
> diff --git a/Documentation/devicetree/bindings/pci/cdns-pcie-host.yaml b/Documentation/devicetree/bindings/pci/cdns-pcie-host.yaml
> new file mode 100644
> index 000000000000..78261bc4f0c5
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/cdns-pcie-host.yaml
> @@ -0,0 +1,30 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/pci/cdns-pcie-host.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Cadence PCIe Host
> +
> +maintainers:
> + - Tom Joseph <tjoseph@cadence.com>
> +
> +allOf:
> + - $ref: "/schemas/pci/pci-bus.yaml#"
> + - $ref: "cdns-pcie.yaml#"
> +
> +properties:
> + vendor-id:
> + description: The PCI vendor ID (16 bits, default is design dependent)
> +
> + device-id:
> + description: The PCI device ID (16 bits, default is design dependent)
While these got defined here as 16-bits, these should be fixed to 32-bit
because they are established properties for a long time.
> +
> + cdns,no-bar-match-nbits:
> + description: Set into the no BAR match register to configure the number
> + of least significant bits kept during inbound (PCIe -> AXI) address
> + translations (default 32)
> + allOf:
> + - $ref: /schemas/types.yaml#/definitions/uint32
What about compatible?
> +
> diff --git a/Documentation/devicetree/bindings/pci/cdns-pcie.yaml b/Documentation/devicetree/bindings/pci/cdns-pcie.yaml
> new file mode 100644
> index 000000000000..497d3dc2e6f2
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/cdns-pcie.yaml
> @@ -0,0 +1,32 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/pci/cdns-pcie.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Cadence PCIe Core
> +
> +maintainers:
> + - Tom Joseph <tjoseph@cadence.com>
> +
> +properties:
> + max-link-speed:
> + minimum: 1
> + maximum: 3
> +
> + num-lanes:
> + minimum: 1
> + maximum: 2
Needs a type.
The Cadence IP can't support x4, x8, or x16?
> +
> + cdns,max-outbound-regions:
> + description: Set to maximum number of outbound regions.
> + allOf:
> + - $ref: /schemas/types.yaml#/definitions/uint32
> +
> + phys:
> + description: List of Generic PHY phandles. One per lane if more than one in
> + the list. If only one PHY listed it must manage all lanes.
> +
> + phy-names:
> + description: List of names to identify the PHY.
> --
> 2.17.1
>
next prev parent reply other threads:[~2020-01-08 3:43 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-06 10:20 [PATCH v2 00/14] Add PCIe support to TI's J721E SoC Kishon Vijay Abraham I
2020-01-06 10:20 ` [PATCH v2 01/14] dt-bindings: PCI: cadence: Add PCIe RC/EP DT schema for Cadence PCIe Kishon Vijay Abraham I
2020-01-08 3:43 ` Rob Herring [this message]
2020-01-08 5:35 ` Kishon Vijay Abraham I
2020-01-16 11:31 ` Kishon Vijay Abraham I
2020-01-06 10:20 ` [PATCH v2 02/14] PCI: cadence: Fix cdns_pcie_{host|ep}_setup() error path Kishon Vijay Abraham I
2020-01-06 10:20 ` [PATCH v2 03/14] linux/kernel.h: Add PTR_ALIGN_DOWN macro Kishon Vijay Abraham I
2020-01-06 10:20 ` [PATCH v2 04/14] PCI: cadence: Add support to use custom read and write accessors Kishon Vijay Abraham I
2020-01-06 10:20 ` [PATCH v2 05/14] PCI: cadence: Add support to start link and verify link status Kishon Vijay Abraham I
2020-01-06 10:20 ` [PATCH v2 06/14] PCI: cadence: Add read/write accessors to perform only 32-bit accesses Kishon Vijay Abraham I
2020-01-06 10:20 ` [PATCH v2 07/14] PCI: cadence: Allow pci_host_bridge to have custom pci_ops Kishon Vijay Abraham I
2020-01-06 10:20 ` [PATCH v2 08/14] PCI: cadence: Add new *ops* for CPU addr fixup Kishon Vijay Abraham I
2020-01-06 10:20 ` [PATCH v2 09/14] PCI: cadence: Fix updating Vendor ID and Subsystem Vendor ID register Kishon Vijay Abraham I
2020-01-06 10:20 ` [PATCH v2 10/14] dt-bindings: PCI: Add host mode dt-bindings for TI's J721E SoC Kishon Vijay Abraham I
2020-01-06 10:20 ` [PATCH v2 11/14] dt-bindings: PCI: Add EP " Kishon Vijay Abraham I
2020-01-06 10:20 ` [PATCH v2 12/14] PCI: j721e: Add TI J721E PCIe driver Kishon Vijay Abraham I
2020-01-06 10:20 ` [PATCH v2 13/14] misc: pci_endpoint_test: Add J721E in pci_device_id table Kishon Vijay Abraham I
2020-01-06 10:20 ` [PATCH v2 14/14] MAINTAINERS: Add Kishon Vijay Abraham I for TI J721E SoC PCIe Kishon Vijay Abraham I
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200108034314.GA5412@bogus \
--to=robh@kernel.org \
--cc=andrew.murray@arm.com \
--cc=arnd@arndb.de \
--cc=bhelgaas@google.com \
--cc=devicetree@vger.kernel.org \
--cc=kishon@ti.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=lorenzo.pieralisi@arm.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox