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[24.155.109.49]) by smtp.gmail.com with ESMTPSA id t13sm6016223otp.33.2020.01.14.17.45.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Jan 2020 17:45:28 -0800 (PST) Received: from rob (uid 1000) (envelope-from rob@rob-hp-laptop) id 2209ae by rob-hp-laptop (DragonFly Mail Agent v0.11); Tue, 14 Jan 2020 19:40:26 -0600 Date: Tue, 14 Jan 2020 19:40:26 -0600 From: Rob Herring To: Kishon Vijay Abraham I Cc: Lorenzo Pieralisi , Bjorn Helgaas , Andrew Murray , Tom Joseph , Arnd Bergmann , Jingoo Han , Gustavo Pimentel , Shawn Lin , Heiko Stuebner , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Jonathan Corbet , Greg Kroah-Hartman , linux-doc@vger.kernel.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH 2/7] dt-bindings: PCI: cadence: Add binding to specify max virtual functions Message-ID: <20200115014026.GA10726@bogus> References: <20191231113534.30405-1-kishon@ti.com> <20191231113534.30405-3-kishon@ti.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20191231113534.30405-3-kishon@ti.com> User-Agent: Mutt/1.10.1 (2018-07-13) Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Tue, Dec 31, 2019 at 05:05:29PM +0530, Kishon Vijay Abraham I wrote: > Add binding to specify maximum number of virtual functions that can be > associated with each physical function. > > Signed-off-by: Kishon Vijay Abraham I > --- > .../devicetree/bindings/pci/cdns,cdns-pcie-ep.txt | 2 ++ > .../devicetree/bindings/pci/ti,j721e-pci-ep.yaml | 8 ++++++++ > 2 files changed, 10 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt > index 4a0475e2ba7e..432578202733 100644 > --- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt > +++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt > @@ -9,6 +9,8 @@ Required properties: > > Optional properties: > - max-functions: Maximum number of functions that can be configured (default 1). > +- max-virtual-functions: Maximum number of virtual functions that can be > + associated with each physical function. > - phys: From PHY bindings: List of Generic PHY phandles. One per lane if more > than one in the list. If only one PHY listed it must manage all lanes. > - phy-names: List of names to identify the PHY. > diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml > index 4621c62016c7..1d4964ba494f 100644 > --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml > +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml > @@ -61,6 +61,12 @@ properties: > minimum: 1 > maximum: 6 > > + max-virtual-functions: > + minItems: 1 > + maxItems: 6 Is there a PCIe spec limit to number of virtual functions per phy function? Or 2^32 virtual functions is okay. > + description: As defined in > + Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt I suspect this this be a common property. > + > dma-coherent: > description: Indicates that the PCIe IP block can ensure the coherency > > @@ -85,6 +91,7 @@ required: > - cdns,max-outbound-regions > - dma-coherent > - max-functions > + - max-virtual-functions > - phys > - phy-names > > @@ -107,6 +114,7 @@ examples: > clock-names = "fck"; > cdns,max-outbound-regions = <16>; > max-functions = /bits/ 8 <6>; > + max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>; > dma-coherent; > phys = <&serdes0_pcie_link>; > phy-names = "pcie_phy"; > -- > 2.17.1 >